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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2008 pc8548e powerquicc iii integrated processor datasheet - preliminary specification features ? embedded e500 core, initial offerings up to 1.2 ghz ? dual dispatch superscalar, 7-stage pipeline design wi th out-of-order issue and execution ? 3065 mips at 1333 mhz (estimated dhrystone 2.1) 36-bit physical addressing enhanced hardware and software debug support double-precision embedded scalar and vector floating-point apus memory management unit (mmu) integrated l1/l2 cache ? l1 cache-32 kb data and 32 kb instruct ion cache with line-locking support ? l2 cache-512 kb (8-way set associative); 512 kb/256 kb/128 kb/64 kb can be used as sram ? l1 and l2 hardware coherency ? l2 configurable as sram, cache and i/o trans actions can be stashed into l2 cache regions integrated ddr memory controller wi th full ecc supp ort, supporting: ? 200 mhz clock rate (400 mhz data rate), 64-bit, 2.5v/2.6v i/o, ddr sdram integrated security engine supporting des, 3des, md-5, s ha-1/2, aes, rsa, rng, kasumi f8/f9 and arc-4 encryption algorithms four on-chip triple-spe ed ethernet controllers (gmacs ) supporting 10- and 100-mbps, and 1-gbps ethernet/ieee*802.3 networks with mii, rmii, gmii, rgmii, rtbi and tbi physical interfaces ? tcp/ip checksum acceleration ? advanced qos features general-purpose i/o (gpio) serial rapidio and pci express high-s peed interconnect interfaces, supporting ? single x8 pci express, or single x4 pci express and single 4x serial rapidio on-chip network (oce an) switch fabric multiple pci interface support ? 64-bit pci 2.2 bus controller (up to 66 mhz, 3.3v i/o) ? 64-bit pci-x bus controller (up to 133 mhz, 3.3v i/o) , or flexibility to configure two 32-bit pci controllers 166 mhz, 32-bit, 3.3v i/o, lo cal bus with memory controller integrated four-channel dma controller dual i2c and dual universal asynchronous receiver/transmitter (duar) support programmable interrup t controller (pic), ieee 1149 .1 jtag test access port 1.1v core voltage with 3.3v an d 2.5v i/o, 783-pin hitce package 0831c?hirel?04/08
2 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 description the pc8548e contains a powerpc ? processor core. the pc8548e integrates a processor that implements the powerpc architecture with system logic required for networking, storage, and general-purpose embedded applications. for func- tional characteristics of the processor, refer to the pc 8548e integrated processor preliminary reference manual. screening full military temperature range (t c = -55c, t j = +125c) industrial temperature range (t c = -40c, t j = +110c) 1. pc8548e architecture general overview figure 1-1. pc8548e block diagram core complex bus x8 pci express 4x rapidlo 66 mhz pci 32-bit 10/100/1gb mii, gmii, tbi, rtbi, rgmii, rmii mii, gmii, tbi, rtbi, rgmii, rmii mii, gmii, tbi, rtbi, rgmii, rmii rtbi, rgmii, rmii irqs sdram ddr flash sdram gpio i 2 c i 2 c i 2 c controller i 2 c controller etsec e500 coherency module ddr/ddr2/ memory controller local bus controller programmable interrupt controller (pic) e500 core 512-kbyte l2 cache/ sram 32-bit pci/ 64-bit pci/pci-x bus interface 32-kbyte l1 instruction cache 32-kbyte l1 data cache ocean switch fabric serial rapidio or pci express 4-channel dma controller pci/pci-x 133 mhz 10/100/1gb 10/100/1gb 10/100/1gb etsec etsec etsec security engine xor engine serial 32-bit pci bus interface (if 64-bit not used) duart tm
3 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 2. features overview the following list provides an overview of the pc8548e feature set: high-performance 32-bit book e?enhanc ed core that implements the powerpc ? architecture ? 32-kbyte l1 instruction cache and 32-kbyte l1 data cache with parity protection. caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. ? signal-processing engine ( spe) apu (auxiliary processing unit). provides an extensive instruction set for vector (64-bit) integer and fractional operations. these instructions use both the upper and lower word s of the 64-bit gprs as they are defined by the spe apu. ? double-precision floating-point apu. provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit gprs. ? 36-bit real addressing ? embedded vector and scalar single-precision floating-point apus. provide an instruction set for single-precision (32-bit) floating-point instructions. ? memory management unit (mmu). especially designed for embedded applications. supports 4-kbyte?4-gbyte page sizes. ? enhanced hardware and software debug support ? performance monitor facility that is similar to, but separate from, the pc8548e performance monitor the e500 defines features that are not implemented on this device. it also generally defines some features that this device implements more specific ally. an understanding of these differences can be critical to ensure proper operations. 512-kbyte l2 cache/sram ? flexible configuration. ? full ecc support on 64-bit boundary in both cache and sram modes ? cache mode supports instruction caching, data caching, or both. ? external masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). ? 1, 2, or 4 ways can be configured for stashing only. ? eight-way set-associative cache organization (32-byte cache lines) ? supports locking entire cache or selected lines. individual line locks are set and cleared through book e instructions or by externally mastered transactions. ? global locking and flash clearing done through writes to l2 configuration registers ? instruction and data locks can be flash cleared separately. ? sram features include the following: ? i/o devices access sram regions by ma rking transactions as snoopable (global). ? regions can reside at any aligned location in the memory map. ? byte-accessible ecc is protected using read-m odify-write transacti on accesses for smaller- than-cache-line accesses. address translation and mapping unit (atmu) ? eight local access windows define mapping within local 36-bit address space. ? inbound and outbound atmus map to larger external address spaces. ? three inbound windows plus a configurat ion window on pci/pci-x and pci express
4 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 ? four inbound windows plus a default window on rapidio ? four outbound windows plus default tr anslation for pci/pci-x and pci express ? eight outbound windows plus default translation for rapidio with segmentation and sub- segmentation support ddr/ddr2 memory controller ? programmable timing suppo rting ddr and ddr2 sdram ? 64-bit data interface ? four banks of memory supported, each up to 4 gbytes, to a maximum of 16 gbytes ? dram chip configurations from 64 mbits to 4 gbits with x8/x16 data ports ? full ecc support ? page mode support ? up to 16 simultaneous open pages for ddr ? up to 32 simultaneous open pages for ddr2 ? contiguous or discontiguous memory mapping ? read-modify-write support for rapidio at omic increment, decrement, set, and clear transactions ? sleep mode support fo r self-refresh sdram ? on-die termination support when using ddr2 ? supports auto refreshing ? on-the-fly power management using cke signal ? registered dimm support ? fast memory access via jtag port ? 2.5v sstl_2 compatible i/o (1.8v sstl_1.8 for ddr2) ? support for battery-backed main memory programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture. ? supports 16 programmable interrupt and processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interrupt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/counters that can generate interrupts ? supports a variety of other internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to external pin for external processing. ? interrupts can be routed to the e500 core?s standard or critical interrupt inputs. ? interrupt summary registers allow fast identification of interrupt source. integrated security engine (sec) optimized to process all the algorithms associated with ipsec, ike, wtls/wap, ssl/tls, and 3gpp ? four crypto-channels, each supporting multi-command descriptor chains ? dynamic assignment of crypto-execution units via an integrated controller
5 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? pkeu: public key execution unit ? rsa and diffie-hellman; programmable field size up to 2048 bits ? elliptic curve cryptography with f 2 m and f(p) modes and programmable field size up to 511 bits ? deu: data encryption standard execution unit ? des, 3des ? two key (k1, k2, k1) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? aesu: advanced encryp tion standard unit ? implements the rijndael symmetric key cipher ? ecb, cbc, ctr, and ccm modes ? 128-, 192-, and 256-bit key lengths ? afeu: arc four execution unit ? implements a stream cipher co mpatible with the rc4 algorithm ? 40- to 128-bit programmable key ? mdeu: message digest execution unit ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? keu: kasumi execution unit ? implements f8 algorithm for encryption and f9 algorithm for integrity checking ? also supports a5/3 and gea-3 algorithms ? rng: random number generator ? xor engine for parity checking in raid storage applications dual i 2 c controllers ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc duart ? two 4-wire interfaces (sin, sout, rts , cts ) ? programming model compatible with the original 16450 uart and the pc16550d local bus controller (lbc) ? multiplexed 32-bit address and data bus operating at up to 133 mhz
6 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. ? three protocol engines available on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with conf igurable bus width (8, 16, or 32 bits) four enhanced three-speed ethernet controllers (etsecs) ? three-speed support (10/100/1000 mbps) ? four ieee 802.3, 802.3u, 80 2.3x, 802.3z, 802.3ac, 802 .3ab compliant controllers ? support for various ethernet physical interfaces: ? 1000 mbps full-duplex ieee 802.3 gm ii, ieee 802.3z tbi, rtbi, and rgmii ? 10/100 mbps full and ha lf-duplex ieee 802.3 mii, ieee 802.3 rgmii, and rmi ? flexible configuration for multip le phy interface configurations. ? tcp/ip acceleration and qos features available ? ip v4 and ip v6 header recognition on receive ? ip v4 header checksum verification and generation ? tcp and udp checksum verification and generation ? per-packet configurable acceleration ? recognition of vlan, stacked (queue in queue) vlan, 802.2, pppoe session, mpls stacks, and esp/ah ip-security headers ? supported in all fifo modes ? quality of service support: ? transmission from up to eight physical queues ? reception to up to eight physical queues ? full- and half-duplex ethernet support (1000 mbps supports only full duplex): ? eee 802.3 full-duplex flow control (autom atic pause frame gener ation or software- programmed pause frame generation and recognition) ? programmable maximum frame le ngth supports jumbo frames (up to 9.6 kb ytes) and ieee 802.1 virtual local area network (vlan) tags and priority ? vlan insertion and deletion ? per-frame vlan control word or default vlan for each etsec ? extracted vlan control word passed to software separately ? retransmission following a collision ? crc generation and verification of inbound/outbound frames ? programmable ethernet preamble insertion and extraction of up to 7 bytes ? mac address recognition: ? exact match on primary and virtual 48-bit unicast addresses
7 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] ? vrrp and hsrp support for seamless router fail-over ? up to 16 exact-match mac addresses supported ? broadcast address (accept/reject) ? hash table match on up to 512 multicast addresses ? promiscuous mode ? buffer descriptors backward compatible with mpc8260 and mpc860t 10/100 ethernet programming models ? rmon statistics support ? 10-kbyte internal transmit and 2-kbyte receive fifos ? mii management interface for control and status ? ability to force allocation of header inform ation and buffer descriptors into l2 cache ocean switch fabric ? full crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with payloads of up to 256 bytes integrated dma controller ? four-channel controller ? all channels accessible by both the local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segment, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enforced coherency (snoop/no snoop) ? ability to start and flow control each dm a channel from extern al 3-pin interface ? ability to launch dma from single write transaction two pci/pci-x controllers ? pci 2.2 and pci-x 1.0 compatible ? one 32-/64-bit pci/pci-x port with support for speeds of up to 133 mhz (maximum pci-x frequency in synchronous mode is 110 mhz) ? one 32-bit pci port with support for speeds from 16 to 66 mhz (available when the other port is in 32-bit mode) ? host and agent mode support ? 64-bit dual address cycle (dac) support ? pci-x supports multip le split transactions ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to-pci and pci-to-memory writes
8 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 ? pci 3.3v compatible ? selectable hardware-enforced coherency serial rapidio interface unit ? supports rapidio interconnect specification, revision 1.2 ? both 1x and 4x lp-serial link interfaces ? long- and short-haul electricals with selectable pre-compensation ? transmission rates of 1.25, 2.5, and 3.125 gbaud (data rates of 1.0, 2.0, and 2.5 gbps) per lane ? auto detection of 1x- and 4x-mode operation during port initialization ? link initialization and synchronization ? large and small size transport information field support selectable at initialization time ? 34-bit addressing ? up to 256 bytes data payload ? all transaction flows and priorities ? atomic set/clr/inc/dec for read-modify-write operations ? generation of io_read_home and flush with data for accessing cache-coherent data at a remote memory system ? receiver-controlled flow control ? error detection, recovery, and time-out for packets and control symbols as required by the rapidio specification ? register and register bit extensions as described in part viii (error management) of the rapidio specification ? hardware recovery only ? register support is not required for software-mediated error recovery. ? accept-all mode of operation for fail-over support ? support for rapidio error injection ? internal lp-serial and application interface-level loopback modes ? memory and phy bist for at-speed production test rapidio?compliant message unit ? 4 kbytes of payload per message ? up to sixteen 256-byte segments per message ? two inbound data message structures within the inbox ? capable of receiving three letters at any mailbox ? two outbound data message structures within the outbox ? capable of sending three letters simultaneously ? single segment multicast to up to 32 devids ? chaining and direct modes in the outbox ? single inbound doorbell message structure ? facility to accept port-write messages pci express interface ? pci express 1.0a compatible
9 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] ? supports x8, x4, x2, and x1 link widths ? auto-detection of number of connected lanes ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing ? 256-byte maximum payload size ? virtual channel 0 only ? traffic class 0 only ? full 64-bit decode wi th 32-bit wide windows pin multiplexing for the high speed i/o interfaces supports one of the following configurations: ? x8 pci express ? x4 pci express and 4x serial rapidio power management ? supports power saving modes: doze, nap, and sleep ? employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-spe cific events ? supports 64 reference events that can be counted on any of the eight counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and ch aining capability ? ability to generate an interrupt on overflow system access port ? uses jtag interface and a tap controlle r to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit streaming of entire block for fast upload and download ieee 1149.1 compliant, jtag boundary scan 783 hitce package 3. electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the pc8548e. this device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 3.1 overall dc electr ical characteristics this section covers the ratings, conditions, and other characteristics.
10 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 3.2 detailed specification this specification descri bes the specific requirements for the microprocessor pc8548e in compliance with e2v standard screening. 3.3 applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: appendix a: general specifications for microcircuits the microcircuits are in accordance with the applicable documents and as specified herein. 3.3.1 absolute maximum ratings table 3-1 provides the absolute maximum ratings. notes: 1. functional and tested operating conditions are given in table 3-2 on page 11 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guarantee d. stresses beyond those listed may affect device reliability or cause permanent damage to the device. table 3-1. absolute maximum ratings (1) characteristic symbol max value unit notes core supply voltage v dd -0.3 to 1.21 v pll supply voltage av dd -0.3 to 1.21 v core power supply for serdes transceivers sv dd -0.3 to 1.21 v pad power supply for serdes transceivers xv dd -0.3 to 1.21 v ddr and ddr2 dram i/o voltage gv dd -0.3 to 2.75 -0.3 to 1.98 v three-speed ethernet i/o, mii management voltage lv dd (for etsec1 and etsec2) -0.3 to 3.63 -0.3 to 2.75 v tv dd (for etsec3 and etsec4) -0.3 to 3.63 -0.3 to 2.75 pci/pci-x, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd -0.3 to 3.63 v (3) local bus i/o voltage bv dd -0.3 to 3.63 -0.3 to 2.75 -0.3 to 1.98 v (3) input voltage ddr/ddr2 dram signals mv in -0.3 to (gv dd + 0.3) v (2)(5) ddr/ddr2 dram reference mv ref -0.3 to (gv dd /2 + 0.3) v (2)(5) three-speed ethernet signals lv in tv in -0.3 to (lv dd + 0.3) -0.3 to (tv dd + 0.3) v (4)(5) local bus signals bv in -0.3 to (bv dd + 0.3) duart, sysclk, system control and power management, i 2 c, and jtag signals ov in -0.3 to (ov dd + 0.3) v (5) pci/pci-x ov in -0.3 to (ov dd + 0.3) v (6) storage temperature range t stg -55 to 150 c
11 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 2. caution: mv in must not exceed gv dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power- on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power- on reset and power-down sequences. 4. caution: l/tv in must not exceed l/tv dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage an d for a maximum duration as shown in figure 3-1 on page 12 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specificat ion for 3.3v operation, as shown in figure 7-1 on page 22 . 3.3.2 recommended operating conditions table 3-2 provides the recommended operating conditions for this device. note that the values in table 3-2 are the recommended and tested operating conditions. proper device operation outside these condi- tions is not guaranteed. notes: 1. this voltage is the input to the filter discussed in section 22.2.1 ?pll power supply filtering? on page 89 and not necessar- ily the voltage at the av dd pin, which may be reduced from v dd by the filter. 2. caution: mv in must not exceed gv dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power- on reset and power-down sequences. table 3-2. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.1v 55 mv v pll supply voltage av dd 1.1v 55 mv v (1) core power supply for serdes transceivers sv dd 1.1v 55 mv v pad power supply for serdes transceivers xv dd 1.1v 55 mv v ddr and ddr2 dram i/o voltage gv dd 2.5v 125 mv 1.8v 90 mv v three-speed ethernet i/o voltage lv dd 3.3v 165 mv 2.5v 125 mv v (4) tv dd 3.3v 165 mv 2.5v 125 mv (4) pci/pci-x, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3v 165 mv v (3) local bus i/o voltage bv dd 3.3v 165 mv 2.5v 125 mv v input voltage ddr and ddr2 dram signals mv in gnd to gv dd v (2) ddr and ddr2 dram reference mv ref gnd to gv dd /2 v (2) three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v (4) local bus signals bv in gnd to bv dd v pci, local bus, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in gnd to ov dd v (3) operating temperature range t c ,t j t c = -55c to t j = 125c c
12 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 3. caution: ov in must not exceed ov dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power- on reset and power-down sequences. 4. caution: l/tv in must not exceed l/tv dd by more than 0.3v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. figure 3-1 shows the undershoot and overshoot voltag es at the interfaces of the pc8548e. figure 3-1. overshoot/undershoot voltage for gv dd /ov dd /lv dd /bv dd note: 1. t clock refers to the clock period associated with the respective interface: for i 2 c and jtag, t clock references sysclk. for ddr, t clock references mclk. for etsec, t clock references ec_gtx_clk125. for lbiu, t clock references lclk. for pci, t clock references pci n _clk or sysclk. for serdes, t clock references sd_ref_clk. 2. please note that with the pci overshoot allowed (as sp ecified above), the device does not fully comply with the maximum ac ratings and device protection gui deline outlined in the pci rev. 2.2 standard (sec- tion 4.2.2.3). the core voltage must always be provided at nominal 1.1v. (see table 3-2 on page 11 for actual recom- mended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 3-2 on page 11 . the input voltage threshold scales with respect to t he associated i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram inter- face uses a single-ended differential receiver referenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the sstl2 electrical signaling standard. gnd gnd ? 0.3v gnd ? 0.7v not to exceed 10% of t clock b/g/l/ov dd + 20% b/g/l/ov dd + 5% b/g/l/ov dd v ih v il (1)
13 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 3.3.3 output driver characteristics table 3-3 provides information on the characteristics of the output driver strengths. the values are pre- liminary estimates. notes: 1. the drive strength of the local bus interface is determined by the conf iguration of the appropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt1 signal at reset. 3. the drive strength of the ddr interf ace in half-strength mode is at t c = 105 c and at gv dd (min). 3.4 power sequencing the device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. these requirements are as follows for power-up: 1. v dd , av dd _ n , bv dd , lv dd , ov dd , sv dd , tv dd , xv dd 2. gv dd all supplies must be at their stable values within 50 ms. notes: 1. items on the same line have no ordering requ irement with respect to o ne another. items on separate lines must be ordered sequentially such that volt age rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. 2. in order to guarantee mcke low during power-up, the above sequencing for gv dd is required. if there is no concern about any of the ddr signals being in an indeterminate state during power-up, then the sequencing for gv dd is not required. table 3-3. output drive capability driver type programmable output impedance ( ? ) supply voltage notes local bus interface utilities signals 25 25 bv dd = 3.3v bv dd = 2.5v (1) 45 (default) 45 (default) bv dd = 3.3v bv dd = 2.5v pci signals 25 ov dd = 3.3v (2) 45 (default) ddr signal 18 36 (half strength mode) gv dd = 2.5v (3) ddr2 signal 18 36 (half strength mode) gv dd = 1.8v (3) tsec/10/100 signals 45 l/tv dd = 2.5/3.3v duart, system control, jtag 45 ov dd = 3.3v i 2 c150ov dd = 3.3v
14 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 4. power characteristics the estimated typical power dissipation for the core complex bus (ccb) versus the core frequency for this family of powerquicc iii devices is shown in table 4-1 . notes: 1. ccb frequency is the soc platform frequency, which corresponds to the ddr data rate. 2. sleep is based on v dd = 1.1 v, t j = 65 c. 3. typical-65 is based on v dd = 1.1 v, t j = 65 c, running dhrystone. 4. typical-105 is based on v dd = 1.1 v, t j = 105 c, running dhrystone. 5. maximum is based on v dd = 1.1 v, t j = 125 c, running a smoke test. at allowable voltage levels, the estimated power dissipation on the 1.1v av dd supplies for the pc8548e plls is shown in table 4-2 . because i/o usage varies from design to design, for power dissipation estimates on the g/l/ov dd power rails, refer to the powerquicc iii i/o power calculator. table 4-1. pc8548e power dissipation (1) ccb frequency (1) core frequency sleep (2) typical-65 (3) typical- 105 (4) maximum (5) unit 400 800 2.7 4.6 7.5 11 w 1000 2.7 5.0 7.9 11.6 1200 2.7 5.4 8.3 11.9 533 1333 6.2 7.9 10.8 12.8 w table 4-2. pc8548e estimated i/o power dissipation interface parameters 1.1v (xv dd )1.8v (gv dd ) 2.5v (b/g/l/tv dd ) 3.3v (b/l/o/tv dd ) comments ddr 266 mhz data 0.31 w 0.59 w 333 mhz data 0.38 w 0.73 w 400 mhz data 0.46 w 533 mhz data 0.60 w pci-express x8, 2.5 g-baud 0.71 w serial rapidio x4, 3.125 g-baud 0.49 w pci-x 64-bit, 133 mhz 0.25 w pci 64-bit, 66 mhz 0.14 w 64-bit, 33 mhz 0.08 w 32-bit, 66 mhz 0.07 w power per pci port 32-bit, 33 mhz 0.04 w local bus 32-bit, 133 mhz 0.14 w 0.24 w 32-bit, 66mhz 0.07 w 0.13 w 32-bit, 33 mhz 0.04 w 0.07 w
15 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 5. input clocks 5.1 system clock timing table 5-1 provides the system clock (sysclk) ac ti ming specifications for the pc8548e. notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such sysclk fre- quency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum operating frequencies. refer to section 20.2 ?ccb/sysclk pll ratio? on page 85 ? and section 20.3 ?e500 core pll ratio? on page 86 , for ratio settings. 2. rise and fall times for sysclk are measured at 0.6v and 2.7v 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter ? short term and long term ? and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be < 500 khz at -20 db. th e bandwidth must cascade-connected pll-based devices to track sysclk drivers with the specified jitter. 6. this parameter has been adjusted slower according to the workaround for device erratum gen-13. 5.2 real time clock timing the rtc input is sampled by the platform clock (ccb clock). the output of the sampling latch is then used as an input to the counters of the pic and the timebase unit of the e500. there is no jitter specifi- cation. the minimum pulse width of the rtc signal should be greater than 2x the period of the ccb clock. that is, minimum clock high time is 2 t ccb , and minimum clock low time is 2 t ccb . there is no minimum rtc frequency; rtc may be grounded if not needed. etsec (10/100/1000 ethernet) mii 0.01 w power per etsec used gmii 0.07 w tbi 0.07 w rgmii 0.04 w rtbi 0.04 w etsec (packet fifo) 16-bit, 200 mhz 0.20 w power per fifo interface used 16-bit, 155 mhz 0.16 w 8-bit, 200 mhz 0.11 w 8-bit, 155 mhz 0.08 w table 4-2. pc8548e estimated i/o power dissipation (continued) interface parameters 1.1v (xv dd )1.8v (gv dd ) 2.5v (b/g/l/tv dd ) 3.3v (b/l/o/tv dd ) comments table 5-1. sysclk ac timing specifications (at re commended oper ating conditions with ov dd = 3.3v 165 mv (see table 3-2 on page 11 ) parameter/condition symbol min typical max unit notes sysclk frequency f sysclk 16 ? 133 mhz (1)(6) sysclk cycle time t sysclk 7.5 ? 60 ns (6) sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns (2) sysclk duty cycle t khk /t sysclk 40 ? 60 % (3) sysclk jitter ? ? ? 150 ps (4)(5)
16 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 5.3 etsec gigabit refe rence clock timing table 5-2 provides the etsec gigabit reference clocks (ec_gtx_clk125) ac timing specifications for the pc8548e. note: 1. rise and fall times for ec_gtx_clk125 are measured from 0.5v and 2.0v for l/tv dd = 2.5v, and from 0.6 and 2.7v for l/tv dd = 3.3v. 2. timing is guaranteed by design and characterization. 3. ec_gtx_clk125 is used to generate the gtx clock tsec n _gtx_clk for the etsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as the phy device can tolerate the duty cycle gener- ated by the tsecn_ gtx_clk. see section 9.2.6 ?rgmii and rtbi ac timing specifications? on page 33 for duty cycle for 10base-t and 100base-t reference clock. 5.4 pci/pci-x refe rence clock timing when the pci/pci-x controller is configured for asynchronous operation, the reference clock for the pci/pci-x controller is not the sysclk input, but instead the pci n _clk. table 5-3 provides the pci/pci-x reference clock ac timing specifications for the pc8548e. notes: 1. rise and fall times for sysclk are measured at 0.6v and 2.7v. 2. timing is guaranteed by design and characterization. table 5-2. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ec_gtx_clk125 frequency f g125 ? 125 ? mhz ec_gtx_clk125 cycle time t g125 ?8?ns ec_gtx_clk125 rise and fall time - l/tv dd = 2.5v - l/tv dd = 3.3v t g125r /t g125f ? 0.75 1.0 ns (1) ec_gtx_clk125 duty cycle - gmii, tbi - 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ?55 53 % (2)(3) table 5-3. pci n _clk ac timing specifications (at recommended operating conditions with ov dd = 3.3v 165 mv (see table 3-2 on page 11 ) parameter/condition symbol min typical max unit notes pci n _clk frequency f pciclk 16 ? 133 mhz pci n _clk cycle time t pciclk 7.5 ? 60 ns pci n _clk rise and fall time t pcikh , t pcikl 0.6 1.0 2.1 ns (1)(2) pci n _clk duty cycle t pcikhkl /t pciclk 40?60% (2)
17 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 5.5 platform to fi fo restrictions please note the following fifo maximum speed restrictions based on platform speed. for fifo gmii mode: fifo tx/rx clock frequency <= platform clock frequency / 4.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 127 mhz for fifo encoded mode: fifo tx/rx clock frequency <= platform clock frequency / 3.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 167 mhz. 5.6 platform frequency requirements fo r pci-express and serial rapidio the ccb clock frequency must be considered for proper operation of the high-speed pci-express and serial rapidio interfaces as described below. for proper pci express operation, the ccb clock frequency must be greater than: for proper serial rapidio operation, the cc b clock frequency must be greater than: 5.7 other input clocks for information on the input clocks of other functi onal blocks of the platform such as serdes, and etsec, see the specific section of this document. 6. reset initialization this section describes the ac electrical specificatio ns for the reset initialization timing requirements of the pc8548e. table 6-1 provides the reset initialization ac ti ming specifications for the ddr sdram component(s). note: 1. sysclk is identical to the pci_clk signal and is the primary clock input for the pc8548e. 500 mhz x (pci-express link width) 8 2 x (0.80) x (serial rapidio interface frequency) x (serial rapidio link width) 64 table 6-1. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s minimum assertion time for sreset 3 ? sysclks (1) pll input setup ti me with stable sysclk before hreset negation 100 ? s input setup time for por configs (ot her than pll config) with respect to negation of hreset 4 ? sysclks (1) input hold time for all por configs (i ncluding pll config) with respect to negation of hreset 2 ? sysclks (1) maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks (1)
18 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 table 6-2 provides the pll lock times. 7. ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the dd r sdram interface of the pc8548e. note that gv dd (typ) = 2.5v for ddr sdram, and gv dd (typ) = 1.8v for ddr2 sdram. 7.1 ddr sdram dc elect rical characteristics table 7-1 provides the recommended operating conditions for the ddr2 sdram controller of the pc8548e when gv dd (typ) = 1.8v. notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0v v out gv dd . table 7-2 provides the ddr capacitance when gv dd (typ) = 1.8v. note: 1. this parameter is sampled. gv dd = 1.8v 0.090v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2v. table 6-2. pll lock times parameter/condition min max unit core and platform pll lock times ? 100 s local bus pll lock time ? 50 s pci/pci-x bus pll lock time ? 50 s table 7-1. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v (1) i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v (2) i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v (3) input high voltage v ih mv ref + 0.125 gv dd + 0.3 v input low voltage v il -0.3 mv ref - 0.125 v output leakage current i oz -50 50 a (4) output high current (v out = 1.420v) i oh -13.4 ? ma output low current (v out = 0.280v) i ol 13.4 ? ma table 7-2. ddr2 sdram capacitance for gv dd (typ)=1.8v parameter/condition symbol min max unit notes input/output capacita nce: dq, dqs, dqs c io 68pf (1) delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf (1)
19 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] table 7-3 provides the recommended operating condit ions for the ddr sdram component(s) when gv dd (typ) = 2.5v. notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0v v out gv dd . table 7-4 provides the ddr capacitance when gv dd (typ) = 2.5v. notes: 1. this parameter is sampled. gv dd = 2.5v 0.125v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2v. table 7-5 provides the current draw characteristics for mv ref . notes: 1. the voltage regulator for mv ref must be able to supply up to 500 a current. table 7-3. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v (1) i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v (2) i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v (3) input high voltage v ih mv ref + 0.15 gv dd + 0.3 v input low voltage v il -0.3 mv ref ? 0.15 v output leakage current i oz -50 50 a (4) output high current (v out = 1.95v) i oh -16.2 ? ma output low current (v out = 0.35v) i ol 16.2 ? ma table 7-4. ddr sdram capacitance for gv dd (typ) = 2.5v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf (1) delta input/output capacitance: dq, dqs c dio ?0.5pf (1) table 7-5. current draw characteristics for mv ref parameter/condition symbol min max unit note current draw for mv ref i mvref ?500a (1)
20 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 7.2 ddr sdram ac elect rical characteristics this section provides the ac electrical characteri stics for the ddr sdram inte rface. the ddr controller supports both ddr1 and ddr2 memori es. ddr1 is supported with th e following ac timings at data rates of 333 mhz. ddr2 is supported with the following ac timings at data rates down to 333 mhz. 7.2.1 ddr sdram input ac timing specifications table 7-6 provides the input ac timing spec ifications for the ddr sdram when gv dd (typ) = 1.8v. table 7-7 provides the input ac timing spec ifications for the ddr sdram when gv dd (typ) = 2.5v. table 7-8 provides the input ac timing specif ications for the ddr sdram interface. notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any cor- responding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew = (t/4 - abs( t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . table 7-6. ddr2 sdram input ac timing specifications for 1.8v interface (at recommended operating conditions) parameter symbol min max unit ac input low voltage v il ? mv ref ? 0.25 v ac input high voltage v ih mv ref + 0.25 v table 7-7. ddr sdram input ac timing specifications for 2.5v interface (at recommended oper- ating conditions) parameter symbol min max unit ac input low voltage v il ? mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 v table 7-8. ddr sdram input ac timing specifications (at recommend ed operating conditions) parameter symbol min max unit notes controller skew for mdqs ? mdq/mecc/mdm t ciskew ps (1)(2) 533 mhz - 300 300 400 mhz - 365 365 333 mhz - 390 390
21 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 7.2.2 ddr sdram output ac timing specifications notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) un til the output went invalid ( ax or dx). for example, t ddkhas symbol- izes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note (1) . for example, tddkhmh describes the ddr timing (dd) from the rising edge of th e mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the mdqs override bits (called wr_data_delay) in the timing_cfg_2 register. this will typically be set to the same delay as in ddr_sdram_clk_cntl[clk_adjust]. the timi ng parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the pc8548e powerquicc iii integrated processor refer- ence manual for a description and understanding of the timing modifications enabled by use of these bits. table 7-9. ddr sdram output ac timing specificatio ns (at recommended operating conditions) parameter symbol (1) min max unit notes mck[n] cycle time, mck [n]/mck[n] crossing t mck 3.75 10 ns (2) addr/cmd output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhas 1.48 1.95 2.40 ? ? ? ns (3) addr/cmd output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhax 1.48 1.95 2.40 ? ? ? ns (3) mcs [n] output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcs 1.48 1.95 2.40 ? ? ? ns (3) mcs [n] output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcx 1.48 1.95 2.40 ? ? ? ns (3) mck to mdqs skew t ddkhmh - 0.6 0.6 ns (4) mdq/mecc/mdm output set up with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhds , t ddklds 538 700 900 ? ? ? ps (5) mdq/mecc/mdm output hold with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhdx , t ddkldx 538 700 900 ? ? ? ps (5) mdqs preamble start t ddkhmp -0.5 t mck ? 0.6 -0.5 x t mck +0.6 ns (6) mdqs epilogue end t ddkhme -0.6 0.6 ns (6)
22 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 5. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[ n] at the pins of the microprocessor. note that t ddkhmp follows the sym- bol conventions described in note (1) . note: for the addr/cmd setup and hold specifications in table 7-9 on page 21 , it is assumed that the clock con- trol register is set to adjust t he memory clocks by 1/2 applied cycle. figure 7-1 on page 22 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 7-1. timing diagram for t ddkhmh figure 7-2 shows the ddr sdram output timing diagram. figure 7-2. ddr sdram output timing diagram mdqs mck[n] mck[n] t mck mdqs t ddkhmh(max) = 0.6 ns t ddkhmh(min) = -0.6 ns addr/cmd mdq[x] mdqs[n] mck[n] mck[n] d1 d0 noop t ddkhdx t ddkldx t ddklds t ddkhds t ddkhmh t ddkhmp t ddkhax , t ddkhcx t ddkhas , t ddkhcs t mck write a0 t ddkhme
23 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 7-3 provides the ac test load for the ddr bus. figure 7-3. ddr ac test load 8. duart this section describes the dc and ac electrical sp ecifications for the duart interface of the pc8548e. 8.1 duart dc electri cal characteristics table 8-1 provides the dc electrical characteristics for the duart interface. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 10 and table 3-2 on page 11 . 8.2 duart ac electrical specifications table 8-2 provides the ac timing parameters for the duart interface. notes: 1. guaranteed by design 2. f ccb refers to the internal platform clock. 3. actual attainable baud rate will be limited by the latency of interrupt processing 4. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subse- quent bit values are sampled each 16 th sample. output z 0 = 50 ? r l = 50 ? gv dd /2 table 8-1. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il - 0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = mn, i oh = -100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v table 8-2. duart ac timing specifications parameter value unit notes minimum baud rate f ccb /1,048,576 baud (1)(2) maximum baud rate f ccb clock/16 baud (1)(2)(3) oversample rate 16 ? (1)(4)
24 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 9. ethernet: enhanced th ree-speed ethernet (e tsec), mii management this section provides the ac and dc electrical characteristic s for enhanced three-speed and mii management. 9.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps) ? gmii/mii/tbi/ rgmi i/rtbi/rmii electri cal characteristics the electrical characteristics s pecified here apply to all gigabi t media independent interface (gmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data input/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5v, while the gmii and tbi interfaces can be operated at 3.3v. the gmii, mii, or tbi interface timing is compliant with the i eee std. 802.3. the rgmi i and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998). the electrical characterist ics for mdio and mdc are specified in section 10. ?ethernet management interface electrical characteristics? on page 36 . 9.1.1 etsec dc electrical characteristics all gmii, mii, tbi, rgmii, rmii and rtbi drivers an d receivers comply with the dc parametric attributes specified in table 9-1 and table 9-2 . the rgmii and rtbi signals are based on a 2.5v cmos interface voltage as defined by jedec eia/jesd8-5. notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in table 3-1 on page 10 and table 3-2 on page 11 table 9-1. gmii, mii, rmii, and tbi dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3v lv dd tv dd 3.13 3.47 v (1)(2) output high voltage (lv dd /tv dd = min, i oh = -4.0 ma) v oh 2.40 lv dd /tv dd + 0.3 v output low voltage (lv dd /tv dd = min, i ol = 4.0 ma) v ol gnd 0.50 v input high voltage v ih 2.0 lv dd /tv dd + 0.3 v input low voltage v il -0.3 0.90 v input high current (v in = lv dd , v in = tv dd ) i ih ?40a (1)(2)(3) input low current (v in = gnd) i il -600 ? a (3)
25 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] . notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in table 3-1 on page 10 and table 3-2 on page 11 . 9.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mi i, tbi, rgmii, rmii and rtbi are presented in this section. 9.2.1 fifo ac specifications the basis for the ac specifications for the etsec?s fifo modes is the double data rate rgmii and rtbi specifications, since they have similar performanc e and are described in a source-synchronous fashion like fifo modes. however, the fifo interface provides deliberate skew between the transmitted data and source clock in gmii fashion. when the etsec is configured for fifo modes, all clocks are supplied from external sources to the rel- evant etsec interface. that is, the transmit cl ock must be applied to the etsecn?s tsecn_tx_clk, while the receive clock must be applied to pin tsecn_rx_clk. the etsec internally uses the transmit clock to synchronously generate transmit data and out puts an echoed copy of the transmit clock back out onto the tsecn_gtx_clk pin (while transmit data appears on tsecn_txd[7:0], for example). it is intended that external receivers capture etsec tr ansmit data using the clock on tsecn_gtx_clk as a source- synchronous timing referenc e. typically, the clock edge that launched the data can be used, since the clock is delayed by the etsec to allow ac ceptable set-up margin at the receiver. note that there is relationship between the maximum fifo s peed and the platform speed. for more information see section 5.5 ?platform to fifo restrictions? on page 17 . table 9-2. rgmii, rtbi and fifo dc el ectrical characteristics parameter symbol min max unit notes supply voltage 2.5v lv dd tv dd 2.37 2.63 v (1)(2) output high voltage (lv dd /tv dd = min, i oh = -1.0 ma) v oh 2lv dd /tv dd + 0.3 v output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol gnd - 0.3 0.40 v input high voltage v ih 1.70 lv dd /tv dd + 0.3 v input low voltage v il -0.3 0.90 v input high current (v in = lv dd , v in = tv dd ) i ih ?10a (1)(2)(3) input low current (v in = gnd) i il -15 ? a (3)
26 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 a summary of the fifo ac specifications appears in table 3-2 and table 9-4 on page 26 . timing diagrams for fifo appear in figure 9-1 and figure 9-2 on page 27 . figure 9-1. fifo transmit ac timing diagram table 9-3. fifo mode transmit ac timing specification parameter/condition symbol min typ max unit tx_clk, gtx_clk clock period t fit 5.0 8.0 100 ns tx_clk, gtx_clk duty cycle t fith/ t fit 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ? ? 250 ps rise time tx_clk (20%?80%) t fitr ?? 0.75 ns fall time tx_clk (80%?20%) t fitf ?? 0.75 ns fifo data txd[7:0], tx_er, tx_en setup time to gtx_clk t fitdv 2.0 ?? ns gtx_clk to fifo data txd[7: 0], tx_er, tx_en hold time t fitdx 0.5 () ? 3.0 ns table 9-4. fifo mode receive ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t fir 5.0 8.0 100 ns rx_clk duty cycle t firh /t fir 45 50 55 % rx_clk peak-to-peak jitter t firj ?? 250 ps rise time rx_clk (20%?80%) t firr ?? 0.75 ns fall time rx_clk (80%?20%) t firf ?? 0.75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t firdx 0.5 ? ? ns t fit t fith t fitf t fitdx txd[7:0] tx_en gtx_clk tx_er t fitdv t fitr
27 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 9-2. fifo receive ac timing diagram 9.2.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 9.2.2.1 gmii transmit ac timing specifications table 9-5 provides the gmii transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock ref- erence (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, i n general, the clock reference symbol representation is based on th ree letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for ri se and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-3 shows the gmii transmit ac timing diagram. figure 9-3. gmii transmit ac timing diagram t fir t firh t firf t firr rx_clk rxd[7:0] rx_dv rx_er valid data t firdx t firdv table 9-5. gmii transmit ac timing specifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ?? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise time (20%-80%) t gtxr (2) ?? 1.0 ns gtx_clk data clock fall time (80%-20%) t gtxf (2) ?? 1.0 ns gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
28 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 9.2.2.2 gmii receive ac timing specifications table 9-6 provides the gmii receive ac timing specifications. . notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letter s representing the clock of a particular functional. for exam- ple, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-4 provides the ac test load for etsec. figure 9-4. etsec ac test load figure 9-5 shows the gmii receive ac timing diagram. figure 9-5. gmii receive ac timing diagram table 9-6. gmii receive ac timing specifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit rx_clk clock period t grx ? 8.0 ? ns rx_clk duty cycle t grxh /t grx 40 ? 60 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ?? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0 ?? ns rx_clk clock rise (20%-80%) t grxr (2) ?? 1.0 ns rx_clk clock fall time (80%-20%) t grxf (2) 1.0 ns lv dd /2 output z 0 = 50 ? r l = 50 ? rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkv rx_dv rx_er
29 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 9.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 9.2.3.1 mii receive ac timing specifications table 9-7 provides the mii transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letter s representing the clock of a particular functional. for exam- ple, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-6 shows the mii transmit ac timing diagram. figure 9-6. mii transmit ac timing diagram table 9-7. mii transmit ac timing specifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit tx_clk clock period 10 mbps t mtx (2) ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35?65% tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1.0 5 15 ns tx_clk data clock rise (20%-80%) t mtxr (2) 1.0 ? 4 ns tx_clk data clock fall (80%-20%) t mtxf (2) 1.0 ? 4 ns tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
30 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 9.2.3.2 mii receive ac timing specifications table 9-8 provides the mii receive ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with re spect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with 2. guaranteed by design. figure 9-7 provides the ac test load for etsec. figure 9-7. etsec ac test load figure 9-8 shows the mii receive ac timing diagram. figure 9-8. mii receive ac timing diagram table 9-8. mii transmit ac timing specifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit rx_clk clock period 10 mbps t mrx (2) ? 400 ? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35?65% rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10 ? ? ns rx_clk clock rise (20%-80%) t mrxr (2) 1.0 ? 4 ns rx_clk clock fall time (80%-20%) t mrxf (2) 1.0 ? 4 ns lv dd /2 output z 0 = 50 ? r l = 50 ? rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf t mrdvkh rx_dv rx_er valid data
31 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 9.2.4 tbi ac timi ng specifications this section describes the tbi transmit and receive ac timing specifications. 9.2.4.1 tbi transmit ac timing specifications table 9-9 provides the tbi transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state )(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit tim- ing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold ti me. note that, in general, the clock reference symbol repre- sentation is based on three letters repr esenting the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-9 shows the tbi transmit ac timing diagram. figure 9-9. tbi transmit ac timing diagram table 9-9. tbi transmit ac timing specifications (a t recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ?? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 1.0 ?? ns gtx_clk rise (20%?80%) t ttxr (2) ?? 1.0 ns gtx_clk fall time (80%?20%) t ttxf (2) ?? 1.0 ns gtx_clk t ttx t ttxh t ttxr t ttxf t ttkhdv tcg[9:0] t ttxf t ttkhdx t ttxr
32 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 9.2.4.2 tbi receive ac timing specifications table 9-10 provides the tbi receive ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) st ate. note that, in general, the clock refer- ence symbol representation is based on thr ee letters representing the clock of a pa rticular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. figure 9-10 shows the tbi receive ac timing diagram. figure 9-10. tbi receive ac timing diagram 9.2.5 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all clocks are supplied from external sources to the rele- vant etsec interface. in single-clock tbi mode, when a 125-mhz tbi receiv e clock is supplied on tsecn pin (no receive clock is used on in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the in all tbi modes. table 9-10. tbi receive ac timing spec ifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit pma_rx_clk[0:1] clock period t trx ? 16.0 ? ns pma_rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns pma_rx_clk[0:1] duty cycle t trxh/ t trx 40 ? 60 % rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ??ns rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.5 ??ns pma_rx_clk[0:1] clock rise time (20%-80%) t trxr (2) 0.7 ? 2.4 ns pma_rx_clk[0:1] clock fall time (80%-20%) t trxf (2) 0.7 ? 2.4 ns valid data valid data pma_rx_clk1 rcg[9:0] t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh t trx
33 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] a summary of the single-clock tbi mode ac specifications for receive appears in table 9-11 . a timing diagram for tbi receive appears in figure 9-11 on page 33 . figure 9-11. tbi single-clock mode rece ive ac timing diagram 9.2.6 rgmii and rtbi ac timing specifications table 9-12 presents the rgmii and rtbi ac timing specifications. notes: 1. note that, in general, the clock reference symbol repres entation for this section is based on the symbols rgt to repres ent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the nota- tion for rise (r) and fall (f) times follows the clock symbol th at is being represented. for sym bols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be ro uted such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. table 9-11. tbi single-clock mode receiv e ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t trrx 7.5 8.0 8.5 ns rx_clk duty cycle t trrh/trrx 40 50 60 % rx_clk peak-to-peak jitter t trrj ? ? 250 ps rise time rx_clk (20%?80%) t trrr ??1.0ns fall time rx_clk (80%?20%) t trrf ??1.0ns rcg[9:0] setup time to rx_clk rising edge t trrdvkh 2.0 ? ? ns rcg[9:0] hold time to rx_clk rising edge t trrdxkh 1.0 ? ? ns rcg[9:0] t trrdvkh t trrdxkh t trrf t trrr t trrx rx_clk t trrh valid data table 9-12. rgmii and rtbi ac timing specifications (at recommended operating conditions with lv dd of 2.5v 5%) parameter/condition symbol (1) min typ max unit data to clock output skew (at transmitter) t skrgt (5) -500 (6) 0500 (6) ps data to clock input skew (at receiver) (2) t skrgt 1.0?2.8ns clock period (3) t rgt (5) 7.288.8ns duty cycle for 10base-t and 100base-tx (3)(4) t rgth /t rgt (5) 40 50 60 % rise time (20%-80%) t rgtr (5) ? ? 0.75 ns fall time (20%-80%) t rgtf (5) ? ? 0.75 ns
34 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transi- tioned between. 5. guaranteed by characterization. 6. in rev 1.0 silicon, due to errata, t skrgt is -650 ps (min) and 650 ps (max). please refer to ?etsec 10? in the device errata document. figure 9-12 on page 34 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 9-12. rgmii and rtbi ac timing and multiplexing diagrams 9.2.7 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 9.2.7.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 9-13 . gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt table 9-13. rmii transmit ac timing specifications (at recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit ref_clk clock period t rmt 15.0 20.0 25.0 ns ref_clk duty cycle t rmth 35 50 65 % ref_clk peak-to-peak jitter t rmtj ?? 250 ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 1.0 ? 10 ns
35 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d ) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letter s representing the clock of a particular functional. for exam- ple, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). figure 9-13 shows the rmii transmit ac timing diagram. figure 9-13. rmii transmit ac timing diagram 9.2.7.2 rmii receive ac timing specifications note: 1. the symbols used for timing specif icationsherein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with re spect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letter s representing the clock of a particular functional. for exam- ple, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). figure 9-14 provides the ac test load for etsec. figure 9-14. etsec ac test load ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er table 9-14. rmii receive ac timing specifications (a t recommended operating conditions with lv dd of 3.3v 5%) parameter/condition symbol (1) min typ max unit ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh 35 50 65 % ref_clk peak-to-peak jitter t rmrj ??250ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup ti me to ref_clk rising edge t rmrdv 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns lv dd /2 output z 0 = 50 ? r l = 50 ?
36 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 9-15 shows the rmii receive ac timing diagram. figure 9-15. rmii receive ac timing diagram 10. ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (manage- ment data input/output) and mdc (management data clock) . the electrical char acteristics for gmii, rgmii, rmii, tbi and rtbi are specified in section 9. ?ethernet: enhanced three-speed ethernet (etsec), mii management? on page 24 . 10.1 mii management dc el ectrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3v. the dc electrical characteristics for mdio and mdc are provided in table 10-1 . note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 10 and table 3-2 on page 11 . r ef_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data table 10-1. mii management dc electrical characteristics parameter symbol min max unit supply voltage (3.3v) ov dd 3.13 3.47 v output high voltage (ov dd = min, i oh = -1 ma) v oh 2.10 ov dd + 0.3 v output low voltage (ov dd = min, i ol = 1 ma) v ol gnd 0.50 v input high voltage v ih 2.0 ? v input low voltage v il ?0.90v input high current (ov dd = max, v in (1) = 2.1v) i ih ?40a input low current (ov dd = max, v in = 0.5v) i il -600 ? a
37 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 10.2 mii management ac electrical specifications table 10-2 provides the mii management ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outpu ts (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) rel- ative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the system clock speed. (the maximum frequency is the maximum platform frequency divided by 64.) 3. this parameter is dependent on the system clock speed. (that is, for a system clock of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a system clock of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz.) 4. guaranteed by design. 5. t plb_clk is the platform (ccb) clock. figure 10-1 shows the mii management ac timing diagram. figure 10-1. mii management interface timing diagram table 10-2. mii management ac timing specifications (at recommended operating conditions with ov dd is 3.3v 5%) parameter/condition symbol (1) min max unit notes mdc frequency f mdc 5.2 8.3 mhz (2)(4) mdc period t mdc 120 192 ns mdc clock pulse width high t mdch 32 ? ns mdc to mdio valid t mdkhdv 16*t ccb ns (5) mdc to mdio delay t mdkhdx 10 16*t ccb ns (3)(5) mdio to mdc setup time t mddvkh 5?ns mdio to mdc hold time t mddxkh 0?ns mdc rise time t mdcr ?10ns (4) mdc fall time t mdhf ?10ns (4) mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (o utput)
38 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 11. local bus this section describes the dc and ac electrical spec ifications for the local bus interface of the pc8548. 11.1 local bus dc electrical characteristics table 11-1 provides the dc electrical characteristic s for the local bus interface operating at bv dd = 3.3v dc note: 1. note that the symbol v in , in this case, represents the bv in symbol referenced in table 3-1 on page 10 and table 3-2 on page 11 . table 11-2 provides the dc electrical characteristic s for the local bus interface operating at bv dd = 2.5v dc. note: 1. note that the symbol v in , in this case, represents the bv in symbol referenced in table 3-1 on page 10 and table 3-2 on page 11 . table 11-1. local bus dc electrical characteristics (3.3v dc) parameter symbol min max unit high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il -0.3 0.8 v input current (v in (1) = 0v or v in = bv dd )i in ? 5a high-level output voltage (bv dd = min, i oh = -2 ma) v oh bv dd - 0.2 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.2v table 11-2. local bus dc electrical characteristics (2.5v dc) parameter symbol min max unit high-level input voltage v ih 1.70 bv dd + 0.3 v low-level input voltage v il -0.3 0.7 v input current (v in (1) = 0v or v in = bv dd ) i ih ? 10 a i il -15 high-level output voltage (bv dd = min, i oh = -1 ma) v oh 2.0 bv dd + 0.3 v low-level output voltage (bv dd = min, i ol = 1 ma) v ol gnd ? 0.3 0.4 v
39 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 11.2 local bus ac elect rical specifications table 11-3 describes the general timing parameters of the local bus interface at bv dd = 3.3v dc. for information about the frequency range of local bus see section 20.1 ?clock ranges? on page 85 . notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state ) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 ? bv dd of the signal in question for 3.3v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is pro- grammed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between comple- mentary signals at bv dd /2. 8. guaranteed by design. table 11-3. local bus general timing parameters (bv dd = 3.3v dc) ? pll enabled parameter symbol (1) min max unit notes local bus cycle time t lbk 7.5 12 ns (2) local bus duty cycle t lbkh /t lbk 43 57 % lclk[n] skew to lclk[m] or lsync_out t lbkskew 150 ps (7)(8) input setup to local bus clock (except lgta /lupwait) t lbivkh1 1.8 ? ns (3)(4) lgta /lupwait input setup to local bus clock t lbivkh2 1.7 ? ns (3)(4) input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.0 ? ns (3)(4) lgta /lupwait input hold from local bus clock t lbixkh2 1.0 ? ns (3)(4) lale output transition to lad/ldp output transition (latch setup and hold time) t lbotot 1.5 ? ns (6) local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.0ns local bus clock to data valid for lad/ldp t lbkhov2 ?2.2ns (3) local bus clock to address valid for lad t lbkhov3 ?2.3ns (3) local bus clock to lale assertion t lbkhov4 2.3 ns (3) output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns (3) output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns (3) local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns (5) local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns (5)
40 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 table 11-4 describes the general timing parameters of the local bus interface at bv dd = 2.5v dc. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 ? bv dd of the signal in question for 3.3v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. figure 9-1 on page 26 provides the ac test load for the local bus. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between comple- mentary signals at bv dd /2. 8. guaranteed by design. table 11-4. local bus timing parameters (bv dd = 2.5v): pll enabled parameter symbol (1) min max unit notes local bus cycle time t lbk 7.5 12 ns (2) local bus duty cycle t lbkh /t lbk 43 57 % lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps (7)(8) input setup to local bus clock (except lgta /lupwait) t lbivkh1 1.9 ? ns (3)(4) lgta /lupwait input setup to local bus clock t lbivkh2 1.8 ? ns (3)(4) input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.1 ? ns (3)(4) lgta /lupwait input hold from local bus clock t lbixkh2 1.1 ? ns (3)(4) lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns (6) local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.1ns local bus clock to data valid for lad/ldp t lbkhov2 ?2.3ns (3) local bus clock to address valid for lad t lbkhov3 ?2.4ns (3) local bus clock to lale assertion t lbkhov4 ?2.4ns (3) output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.8 ? ns (3) output hold from local bus clock for lad/ldp t lbkhox2 0.8 ? ns (3) local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.6ns (5) local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.6ns (5)
41 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 11-1 provides the ac test load for the local bus. figure 11-1. local bus ac test load note: pll bypass mode is recommended when lbiu frequency is at or below 83 mhz. when lbiu operates above 83 mhz, lbiu pll is recommended to be enabled. figure 11-2 to figure 11-7 on page 47 show the local bus signals. figure 11-2. local bus signals, (pll enabled) bv dd /2 output z 0 = 50 ? r l = 50 ? output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4 lupwait
42 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 table 11-5 describes the timing parameters of the local bus interface at bv dd = 3.3v with pll disabled. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which preceeds lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between comple- mentary signals at bv dd /2. 4. all signals are measured from bv dd /2 of the rising edge of local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. 9. guaranteed by design. table 11-5. local bus timing parameters: pll bypassed parameter symbol (1) min max unit notes local bus cycle time t lbk 12 ? ns (2) local bus duty cycle t lbkh /t lbk 43 57 % internal launch/capture clock to lclk delay t lbkhkt 2.3 4.4 ns (8) input setup to local bus clock (except lgta /lupwait) t lbivkh1 6.2 ? ns (4)(5) lgta /lupwait input setup to local bus clock t lbivkl2 6.1 ? ns (4)(5) input hold from local bus clock (except lgta /lupwait) t lbixkh1 -1.8 ? ns (4)(5) lgta /lupwait input hold from local bus clock t lbixkl2 -1.3 ? ns (4)(5) lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns (6) local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? -0.3 ns local bus clock to data valid for lad/ldp t lbklov2 ? -0.1 ns (4) local bus clock to address valid for lad t lbklov3 ? 0ns (4) output hold from local bus clock (except lad/ldp and lale) t lbklox1 -3.7 ? ns (4) output hold from local bus clock for lad/ldp t lbklox2 -3.7 ? ns (4) local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ? 0.2 ns (7) local bus clock to output high impedance for lad/ldp t lbkloz2 ? 0.2 ns (7)
43 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 11-3. local bus signals (pll bypass mode) note: in pll bypass mode, lclk[n] is the inverted version of the internal clock with the delay of t lbkhkt . in this mode, signals are launched at the rising edge of the internal clock and are captur ed at falling edge of the internal clock withe the exception of lgta /lupwait (which is captured on on the rising edge of the internal clock). output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4 lupwait
44 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 11-4. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 gpcm mode input signal: lgta
45 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 11-5. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) t lbivkh1 t lbixkl2 internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
46 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 11-6. local bus signals, gpcm/upm signals for lccr[clkdiv] = 8 or 16 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] gpcm mode input signal: lgta
47 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 11-7. local bus signals, gpcm/upm signals for lccr[clkdiv] = 8 or 16 (pll bypass mode) 12. programmable in terrupt controller in irq edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at lest 3 system clocks (sysclk periods). t lbixkl2 t lbivkh1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
48 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 13. jtag this section describes the dc and ac electrical specificatio ns for the ieee std. 11 49.1 (jtag) interface of the pc8548e. 13.1 jtag dc electrical characteristics table 13-1 provides the dc electrical characteristics for the jtag interface. note: 1. note that the symbol v in , in this case, represents the ov in . 13.2 jtag ac electri cal specifications table 13-2 provides the jtag ac timing specifications as defined in figure 13-2 through figure 13-4 on page 50 . table 13-1. jtag dc electrical characteristics parameter symbol (2) min max unit high-level input voltage v ih 2.0 ov dd + 0.3 v low-level input voltage v il -0.3 0.8 v input current (v in (1) = 0 v or v in = v dd ) i in ?5a high-level output voltage (ov dd = min, i oh = -2 ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v table 13-2. jtag ac timing specificatio ns (independent of sysclk) (1) parameter symbol (2) min max unit notes jtag external clock frequency of operation f jtg 033.3mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02.0ns (6) trst assert time t trst 25 ? ns (3) input setup times: - boundary-scan data - tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns (4) input hold times: - boundary-scan data - tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns (4)
49 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] notes: 1. all outputs are measured from the mid point voltage of the falling/rising edge of t tclk to the midpoint of t he signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 13-1 on page 49 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. figure 13-1 provides the ac test load for tdo and the boundary-scan outputs. figure 13-1. ac test load for the jtag interface figure 13-2 provides the jtag clock input timing diagram. figure 13-2. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2). valid times: - boundary-scan data - tdo t jtkldv t jtklov 4 4 20 25 ns (5) output hold times: - boundary-scan data - tdo t jtkldx t jtklox 30 30 ns (5) jtag external clock to output high impedance: - boundary-scan data - tdo t jtkldz t jtkloz 3 3 19 9 ns (5)(6) table 13-2. jtag ac timing specificatio ns (independent of sysclk) (1) (continued) parameter symbol (2) min max unit notes ov dd /2 output z 0 = 50 ? r l = 50 ? vm vm vm t jtg t jtgr t jtgf t jtkhkl jtag external clock
50 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 13-3 provides the trst timing diagram. figure 13-3. trst timing diagram note: vm = midpoint voltage (ov dd /2). figure 13-4 provides the boundary-scan timing diagram. figure 13-4. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2). 14. i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the pc8548e. 14.1 i 2 c dc electrical characteristics table 14-1 provides the dc electrical characteristics for the i 2 c interface. notes: 1. output voltage (open drain or open co llector) condition = 3 ma sink current. 2. refer to the pc8548e powerquicc iii integrated host processor reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. trst t trst vm vm vm jtag external clock boundary data inputs boundary data outputs boundary data outputs t jtdxkh t jtdvkh t jtkldv t jtkldz output data valid t jtkldx vm input data valid output data valid table 14-1. i 2 c dc electrical characteristics (at recommended operating conditions with ov dd of 3.3v 5%) parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v input low voltage level v il -0.3 0.3 ov dd v low level output voltage v ol 0 0.2 ov dd v (1) pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns (2) input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i -10 10 a (3) capacitance for each i/o pin c i ?10pf
51 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 14.2 i 2 c ac electrical specifications table 14-2 provides the ac timing parameters for the i 2 c interfaces. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c tim- ing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp ri- ate letter: r (rise) or f (fall). 2. pc8548e provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. as a transmitter, the pc8548e provides a delay time of at least 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unin- tended generation of start or stop condition. when pc8548eacts as the i 2 c bus master while transmitting, pc8548e drives both scl and sda. as long as the load on scl and sda ar e balanced, pc8548e would not cause unintended generation of start or stop condition. therefore, the 300 ns sda output delay time is not a conc ern. if, under some rare condition, the 300 ns sda output delay time is required for pc8548e as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved, assuming that the desired i 2 c scl clock frequency is 400 khz and the digital filter sampling rate register (i2cdfsrr) is programmed with its default setting of 0x10 (decimal 16): table 14-2. i 2 c ac electrical specificati ons (all values refer to v ih (min) and v il (max) levels (see table 14-1 ) parameter symbol (1) min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl (5) 1.3 ? s high period of the scl clock t i2ch (5) 0.6 ? s setup time for a repeated start condition t i2svkh (5) 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl (5) 0.6 ? s data setup time t i2dvkh (5) 100 ? ns data hold time: - cbus (4) compatible masters - i 2 c bus devices t i2dxkl ? 0 (2) ? 0.9 (3) s set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd v i 2 c source clock frequency 333 mhz 266 mhz 200 mhz 133 mhz fdr bit setting 0x2a 0x05 0x26 0x00 actual fdr divider selected 896 704 512 384 actual i 2 c scl frequency generated 371 khz 378 khz 390 khz 346 khz
52 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 for the detail of i 2 c frequency calculation, refer to the application note an2919 ?determining the i 2 c fre- quency divider ratio for scl?. note that the i 2 c source clock frequency is half of the ccb clock frequency for mpc8548e. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. 5. guaranteed by design. figure 14-1 provides the ac test load for the i 2 c. figure 14-1. i 2 c ac test load figure 14-2 shows the ac timing diagram for the i 2 c bus. figure 14-2. i 2 c bus ac timing diagram 15. pci/pci-x table 15-1 on page 52 describes the dc and ac electrical spec ifications for the pci/pci-x bus of the pc8548e. note that the maximum pci-x frequency in synchronous mode is 110 mhz. 15.1 pci/pci-x dc elect rical characteristics table 15-1 provides the dc electrical characteristics for the pci/pci-x interface. notes: 1. ranges listed do not meet the fu ll range of the dc specifications of the pci 2.2 local bus specifications . 2. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 10 and table 3-2 on page 11 . ov dd /2 output z 0 = 50 ? r l = 50 ? sr s sda scl t i2svkh t i2khkl ps t i2cf t i2cl t i2sxkl t i2dxkl , t i2ovkl t i2ch t i2dvkh t i2sxkl t i2cr t i2cf t i2pvkh table 15-1. pci/pci-x dc electrical characteristics (1) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il -0.3 0.8 v input current (v in (2) = 0v or v in = v dd )i in ? 5a high-level output voltage (ov dd = min, i oh = -100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2v
53 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 15.2 pci/pci-x ac el ectrical specifications this section describes the general ac timing parameters of the pci/pci-x bus. note that the clock refer- ence clk is represented by sysclk when the pci contro ller is configured fo r asynchronou s mode and by pci n _clk when it is configured for asynchronous mode. table 15-2 provides the pci ac timing specifications at 66 mhz. notes: 1. note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (refer- ence)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci/pci-x timing (pc) with respect to the time the input signal s (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci/pci-x timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications. 3. all pci signals are measured from ov dd /2 of the rising edge of pci_sync_in to 0.4 ? ov dd of the signal in question for 3.3v pci signaling levels. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. 6. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 20. ?clocking? on page 85 . 7. the setup and hold time is with respect to the rising edge of hreset . 8. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the mi nimum of 5 clocks in the pci 2.2 local bus specifications. 9. the reset assertion timing requirement for hreset is 100 ? s. 10. guaranteed by characterization. 11. guaranteed by design. figure 15-1 provides the ac test load for pci and pci-x. figure 15-1. pci/pci-x ac test load table 15-2. pci ac timing specifications at 66 mhz parameter symbol (1) min max unit notes sysclk to output valid t pckhov ?6ns (2)(3) output hold from sysclk t pckhox 2?ns (2)(10) sysclk to output high impedance t pckhoz ?14ns (2)(4)(11) input setup to sysclk t pcivkh 3?ns (2)(5)(10) input hold from sysclk t pcixkh 0?ns (2)(5)(10) req64 to hreset (9) setup time t pcrvrh 10 t sys ?clocks (6)(7)(11) hreset to req64 hold time t pcrhrx 050ns (7)(11) hreset high to first frame assertion t pcrhfv 10 ? clocks (8)(11) ov dd /2 output z 0 = 50 ? r l = 50 ?
54 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 15-2 shows the pci/pci-x input ac timing conditions. figure 15-2. pci/pci-x input ac timing measurement conditions figure 15-3 shows the pci/pci-x output ac timing conditions. figure 15-3. pci/pci-x output ac timing measurement condition table 15-3 provides the pci-x ac timi ng specifications at 66 mhz. notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. t pcivkh clk input t pcixkh clk high-impedance output output delay t pckhov t pckhoz table 15-3. pci-x ac timing specifications at 66 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ?3.8ns (1)(2)(3)(7)(8) output hold from sysclk t pckhox 0.7 ? ns (1)(10) sysclk to output high impedance t pckhoz ?7ns (1)(4)(8)(11) input setup time to sysclk t pcivkh 1.7 ? ns (3)(5) input hold time from sysclk t pcixkh 0.5 ? ns (10) req64 to hresetsetup time t pcrvrh 10 ? clocks (11) hreset to req64 hold time t pcrhrx 050ns (11) hreset high to first frame assertion t pcrhfv 10 ? clocks (9)(11) pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks (11) hreset to pci-x initializatio n pattern hold time t pcrhix 050ns (6)(11)
55 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern contro l signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specif ied in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independe nt of how many outputs switch simultaneously. 9. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci-x 1.0a specification. 10. guaranteed by characterization. 11. guaranteed by design. table 15-4 provides the pci-x ac timing specifications at 133 mhz. note that the maximum pci-x frequency in synchronous mode is 110 mhz. notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern contro l signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specif ied in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independe nt of how many outputs switch simultaneously. 9. the timing parameter t pcivkh is a minimum of 1.4 ns rather t han the minimum of 1.2 ns in the pci-x 1.0a specification. 10. the timing parameter t pcrhfv is a minimum of 10 clocks rather t han the minimum of 5 clocks in the pci-x 1.0a specification. 11. guaranteed by characterization. 12. guaranteed by design. table 15-4. pci-x ac timing specifications at 133 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ?3.8ns (1)(2)(3)(7)(8) output hold from sysclk t pckhox 0.7 ? ns (1)(11) sysclk to output high impedance t pckhoz ?7ns (1)(4)(8)(12) input setup time to sysclk t pcivkh 1.2 ? ns (3)(5)(9)(11) input hold time from sysclk t pcixkh 0.5 ? ns (11) req64 to hreset setup time t pcrvrh 10 ? clocks (12) hreset to req64 hold time t pcrhrx 050ns (12) hreset high to first frame assertion t pcrhfv 10 ? clocks (10)(12) pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks (12) hreset to pci-x initializatio n pattern hold time t pcrhix 050ns (6)(12)
56 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 16. high-speed interfaces this section describes the common dc electrical specifications for the high-speed interconnect inter- faces (serial rapidio and pci express) of the pc8548e. 16.1 dc requirements for se rdes reference clocks the serdes reference clocks are sd_ref_clk and sd_ref_clk . recommended minimum operating voltage is -0.4v; recommended maximum operating voltage is 1.32v; maximum absolute voltage is 1.72v. each differential clock input has an internal 50 ? termination to gnd. the reference clock must be able to drive this termination. the input is ac-coupled on chip following the termination. the amplitude of the clock must be at least a 400 mv differential peak-peak for single-ended clock. if driven differentially, each signal wire needs to drive 100 mv around common mode voltage. the differential reference clock (sd_ref_clk/sd_ref_clk ) input is hcsl compatible dc coupled or lvds compatible with ac coupling. figure 16-1. driver and receiver of serdes (p ci express, serial rapidio, and sd_ref_clk/sd_ref_clk 16.2 spread spectrum clock sd_ref_clk/sd_ref_clk_b was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30?33 khz rate is allowed), assuming both ends have same reference clock. for better results use a source without significant unintended modulation. 17. pci express this section describes the dc and ac electrical s pecifications for the pci express bus of the pc8548e. 17.1 dc requirements for pci e xpress sd_ref_clk and sd_ref_clk for more information, see section 16.1 ?dc requirements for serdes reference clocks? on page 56 . 50 ? 50 ? sd_tx n sd_tx n input amp 50 ? 50 ? sd_ref_clk/ sd_rx n sd_ref_clk/ sd_rx n output driver
57 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 17.2 ac requirements for pci express serdes clocks table 17-1 lists ac requirements. note: 1. typical based on pci express specification 2.0. 17.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate t hat is within 600 parts per million 15 (ppm) of each other at all times. this is specified to allow bit rate clock sources with a 300 ppm tolerance. 17.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of t he transport and data link layer please use the pci express base specification. rev. 1.0a document. 17.4.1 differential transmitter (tx) output table 17-2 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 17-1. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typical max units notes t ref refclk cycle time - 10 - ns (1) t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ??100ps? t refpj phase jitter. deviation edge location in edge location with respect to mean - 50 ?50ps? table 17-2. differential transmitter (t x) output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v tx-diffp-p differential peak-to- peak output voltage 0.8 1.2 v v tx-diffp-p = 2*|v tx-d+ - v tx-d- | see note (2) . v tx-de-ratio de- emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the vtx-diffp-p of the first bit after a transition. see note (2) . t tx-eye minimum tx eye width 0.70 ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 - t tx-eye = 0.3 ui. see notes (2) and (3) . t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median. 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consec utive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2) and (3) .
58 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 t tx-rise, ttx- fall d+/d- tx output rise/fall time 0.125 ui see notes (2) and (4) v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-acp = rms(|v txd+ - v txd -|/2 -v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 see note (2) v tx-cm-dc- active-idle- delta absolute delta of dc common mode voltage during lo and electrical idle 0100mv | vtx-cm-dc (during lo) - v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 [lo] v tx-cm-idle-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 [electrical idle] see note (2) . v tx-cm-dc-line- delta absolute delta of dc common mode between d+ and d? 025mv | vtx-cm-dc-d+ - v tx-cm-dc-d- | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | see note (2) . v tx-idle-diffp electrical idle differential peak output voltage 020mv v tx-idle-diffp = |v tx-idle-d+ -v tx-idle-d- | <= 20 mv see note (2) . v tx-rcv-detect the amount of voltage change allowed during receiver detection 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note (5) . v tx-dc-cm the tx dc common mode voltage 03.6v the allowed dc common mode voltage under any conditions. see note (5) . i tx-short tx short circuit current limit 90 ma the total current the transmitter can provide when shorted to its ground t tx-idle-min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit afte r successfully receiving an electrical idle ordered set t tx-idle-set-to- idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 20 ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from lo. t tx-idle-to- diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle rl tx-diff differential return loss 12 db measured over 50 mhz to 1.25 ghz. see note (3) rl tx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz. see note (3) z tx-diff-dc dc differential tx impedance 80 100 120 ? tx dc differential mode low impedance table 17-2. differential transmitter (tx) outp ut specifications (continued) symbol parameter min nom max units comments
59 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timi ng and voltage compliance test load as shown in figure 17-3 on page 63 and measured over any 250 consecutive tx uis. (also re fer to the transmitter compliance eye diagram shown in figure 17-1 on page 60 .) 3. a t tx-eye = 0.70 ui provides for a total sum of dete rministic and random jitter budget of t tx-jitter-max = 0.30 ui for the trans- mitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted t hat the median is not the sa me as the mean. the jitter median describes the point in time where th e number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. th is input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 ? to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 ? probes; see figure 17-3 on page 63 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20-80% at transmitter package pins into a test load as shown in figure 17-3 on page 63 for both v tx-d+ and v tx-d- . 6. see section 4.3.1.8 of the pci expr ess base specifications rev 1.0a. 7. see section 4.2.6.3 of the pci expr ess base specifications rev 1.0a. 17.4.2 transmitter comp liance eye diagrams the tx eye diagram in figure 17-1 on page 60 is specified using the passive compliance/test measure- ment load (see figure 17-3 on page 63 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: it is recommended that the recovered tx ui is ca lculated using all edges in the 3500 consecutive ui inter- val with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits). z tx-dc transmitter dc impedance 40 ? required tx d+ as wellall states l tx-skew lane-to-lane output skew 500 + 2 ui ps static skew between any two transmitter lanes within a single link c tx ac coupling capacitor 75 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. t crosslink crosslink random timeout 01ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note (6) . table 17-2. differential transmitter (tx) outp ut specifications (continued) symbol parameter min nom max units comments
60 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 figure 17-1. minimum transmitter timing and voltage output compliance specifications 17.4.3 differential receiver (rx) input specifications table 17-3 defines the specifications for the differential i nput at all receivers (rxs). the parameters are specified at the component pins. v tx-diff = 0 mv (d+ d- crossing point) v tx-diff = 0 mv (d+ d- crossing point) (transition bit) v tx-diffp-p-min = 800 mv (de-emphasized bit) 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) .07 ui = ui - 0.3 ui(j tx-total-max ) (transition bit) v tx-diffp-p-min = 800 mv table 17-3. differential receiver (r x) input specifications symbol parameter min nom max units comments ui unit interval 399.8 8 400 400.1 2 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v rx-diffp-p differential peak-to- peak output voltage 0.175 1.200 v v rx-diffp-p = 2*|v rx-d+ - v rx-d- | see note (2) . t rx-eye minimum receiver eye width 0.4 ui t he maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max- jitter = 1 - t rx-eye = 0.6 ui. see notes (2) and (3) . t rx-eye-median-to-max - jitter maximum time between the jitter median and maximum deviation from the median 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2)(3)(7) .
61 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement poi nt and measured over any 250 c onsecutive uis. the test load in figure 17-3 on page 63 should be used as the rx device when taking measurements (a lso refer to the receiver compliance eye diagram shown in figure 17-2 on page 62 ). if the clocks to the rx and tx are not derived fr om the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui determinis tic and random jitter budget for the transmitter and inter- connect collected any 250 consecutive uis. the trx-eye- median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget col - lected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the aver- aged time value. if the clocks to the rx and tx are not deriv ed from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-acp = |v rxd+ - v rxd- |/2 - v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ - v rx-d- |/2 see note (2) rl rx-diff differential return loss 15 db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at +300 mv and -300 mv, respectively. see note (4) rl rx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at 0v. see note (4) z rx-diff-dc dc differential input impedance 80 100 120 ? rx dc differential (5) z rx-dc dc input impedance 40 50 60 ? required rx d+ as well as d-dc impedance (50 20% tolerance). see notes (2) and (5) z rx-high-imp-dc powered down dc input impedance 200 k ? required rx d+ as well as d-dc impedance when the receiver terminations do not have power. see note (6) v rx-idle-det-diffp-p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ -v rx-d- | measured at the package pins of the receiver t rx-idle-det-diff- entertime unexpected electrical idle enter detect threshold integration time 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. l tx-skew to t a l s ke w 2 0 n s skew across all lanes on a link. this includes variation in the length of skp ordered set (e.g. com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. table 17-3. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
62 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 4. the receiver input impedance shall result in a differential re turn loss greater than or equal to 15 db with the d+ line biase d to 300 mv and the d- line biased to -300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requ irement applies to all valid input levels. the reference impedance for return loss measurements for is 50 ? to ground for both the d+ and d- line (that is, as mea- sured by a vector network analyzer with 50 ? probes - see figure 17-3 on page 63 ). note: that the series capacitors ctx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (t he initial state of the ltssm) there is a 5 ms transition time before receiver terminatio n values must be met on all un-configured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental re set is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo- rithm using a minimization merit function. least squares and me dian deviation fits have worked well with experimental and simulated data. 17.5 receiver compli ance eye diagrams the rx eye diagram in figure 17-2 on page 62 is specified using the passive compliance/test measure- ment load (see figure 17-3 on page 63 ) in place of any real pci express rx component. note: in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 17-3 on page 63 ) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance fr om the compliance/test measurement load. the input receiver eye diagram is implementation specific and is not specified. rx component designer should pro- vide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 17-2 ) expected at the input receiver based on so me adequate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: the reference impedance for return loss measurements is 50. to ground for both the d+ and d- line (i.e., as measured by a vector network analyzer with 50. probes; see figure 17-3 on page 63 ). note that the series capacitors, ctx, are optional for the return loss measurement. figure 17-2. minimum receiver eye timing and voltage compliance specification v rx-diff = 0 mv (d+ d- crossing point) v rx-diff = 0 mv (d+ d- crossing point) 0.4 ui = t rx-eye-min v rx-diffp-p-min > 175 mv
63 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 17.5.1 compliance test and measurement load the ac timing and voltage parameters must be verifi ed at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 17-3 on page 63 . note: the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowl- edge that package/board routing may benefit from d+ and d? not being exactly matched in length at the package pin boundary. figure 17-3. compliance test/measurement load 18. serial rapidio this section describes the dc and ac electrical specifications for t he rapidio interface of the pc8548e, for the lp-serial physical layer. the electrical s pecifications cover both single and multiple-lane links. two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors across a backp lane. a single receiver specificat ion is given that will accept sig- nals from both the short run and long run transmitter specifications. the short run transmitter should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. this co vers the case where connections are made to a mez- zanine (daughter) card. the minimum swings of the short run specification reduce the overall power used by the transceivers. the long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. this allows a user to drive signals across two connectors and a backplane. the specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a tolerance of 100 ppm. the worst case frequency difference between any transmit and re ceive clock will be 200 ppm. to ensure interoperability between drivers and receivers of differ ent vendors and technologies, ac cou- pling at the receiver input must be used. 18.1 dc requirements for serial rapidio sd_ref_clk and sd_ref_clk for more information, see section 16.1 ?dc requirements for serdes reference clocks? on page 56 . d+ package pin d- package pin tx silicon + package r = 50 ? r = 50 ? c = c tx c = c tx
64 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 18.2 ac requirements for serial rapidio sd_ref_clk and sd_ref_clk table 18-1 lists ac requirements. 18.3 signal definitions lp-serial links use differential signaling. this section defines terms used in the description and specifica- tion of differential signals. figure 18-1 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using thes e waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd and rd each have a peak-to-peak swing of a - b volts 2. the differential output signal of the transmitter, v od , is defined as v td -v td 3. the differential input signal of the receiver, v id , is defined as v rd -v rd 4. the differential output signal of the transmitter and the differential input signal of the receiver each range from a - b to -(a - b) volts 5. the peak value of the differential transmitter out put signal and the differential receiver input sig- nal is a - b volts 6. the peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (a - b) volts figure 18-1. differential peak-peak voltage of transmitter or receiver to illustrate these definitions using real values, consider th e case of a cml (current mode logic) trans- mitter that has a common mode voltage of 2.25v and each of its outputs, td and td , has a swing that goes between 2.5v and 2.0v. usin g these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signal ra nges between 500 mv and -500 mv. the peak differ- ential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mv p-p. table 18-1. sd n_ref_clk and sdn_ref_clk ac requirements symbol parameter description mi n typical max units comments t ref refclk cycle time ? 10(8) ? ns 8 ns applies only to serial rapidio with 125-mhz reference clock t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ?? 80 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location - 40 ? 40 ps a volts b volts td or rd td or rd differential peak-peak = 2 x (a-b)
65 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 18.4 equalization with the use of high speed serial links, the inte rconnect media will caus e degradation of th e signal at the receiver. effects such as inter-symbol interference (i si) or data dependent jitter are produced. this loss can be large enough to degrade the eye opening at t he receiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the most common equalization tech- niques that can be used are: a passive high pass filter network placed at the receiver. this is often referred to as passive equalization. the use of active circuits in the receiver. this is often referred to as adaptive equalization. 18.5 explanatory note on tran smitter and receiver specifications ac electrical specifications are given for transmitte r and receiver. long run and short run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications ar e guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to serial rapidio, as described in section 9.1 ?enhanced three- speed ethernet controller (etsec) (10/100/1gb mbps) ? gmii/mii/tbi/ rgmii/rtbi/rmii electrical characteristics? on page 24 . the goal of this standard is that elec trical designs for serial rapidio can reuse electrical designs for xaui, suitably modifi ed for applications at the baud intervals and reaches described herein. 18.6 transmitter specifications lp-serial transmitter electrical and timing specifications are stated in the text and tables of this section. the differential return loss, s11, of the transmitter in each case shall be better than -10 db for (baud frequency)/10 < freq(f) < 625 mhz, and -10 db + 10log(f/625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differential return loss measurements is 100 ? resistive. differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20% - 80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb and 15 ps at 3.125 gb.
66 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 table 18-2. short run transmitter ac timing specifications: 1.25 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 18-3. short run transmitter ac timing specifications: 2.5 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 18-4. short run transmitter ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm
67 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] table 18-5. long run transmitter ac timing specifications: 1.25 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 18-6. long run transmitter ac timing specifications: 2.5 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 18-7. long run transmitter ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm
68 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 for each baud rate at which an lp-serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in figure 18-2 with the parameters specified in table 18-8 when measured at the output pins of the device and the device is driving a 100 ? 5% differential resistive load. the output eye pattern of an lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol inter- ference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. figure 18-2. transmitter output compliance mask table 18-8. transmitter differential output eye diagram parameters transmitter type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud short range 250 500 0.175 0.39 1.25 gbaud long range 400 800 0.175 0.39 2.5 gbaud short range 250 500 0.175 0.39 2.5 gbaud long range 400 800 0.175 0.39 3.125 gbaud short range 250 500 0.175 0.39 3.125 gbaud long range 400 800 0.175 0.39 0 time in ui 0 1 a b 1-b 1-a transmitter differential output voltage v diff max -v diff max -v diff min v diff min
69 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 18.7 receiver s pecifications lp-serial receiver electrical and timing specifications are stated in the text and tables of this section. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8)*(baud frequency). this includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. ac coupling components are included in this requirement. the reference impedance for return loss measurements is 100 ? resistive for different ial return loss and 25 ? resistive for common mode. note: 1. total jitter is composed of three components, determinist ic jitter, random jitter and single frequency sinusoidal jitter . the sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 18-3 on page 70 . the sinusoidal jit- ter component is included to ensure margin for low frequen cy jitter, wander, noise, crosstalk and other variable system effects. note: total jitter is composed of three components, determinis tic jitter, random jitter and single frequency sinusoidal jitter. the sinuso- idal jitter may have any amplitude and frequency in the unshaded region of figure 18-3 on page 70 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. table 18-9. receiver ac timing spec ifications ? 1.25 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 800 800 ps 100 ppm table 18-10. receiver ac timing s pecifications: 2.5 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 400 400 ps 100 ppm
70 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 note: 1. total jitter is composed of three components, determinist ic jitter, random jitter and single frequency sinusoidal jitter . the sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 18-3 . the sinusoidal jitter compo- nent is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects figure 18-3. single frequency sinusoidal jitter limits table 18-11. receiver ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 22 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 320 320 ps 100 ppm frequency 22.1 khz 1.875 mhz 20 mhz sinuso?dal jitter amplitude 8.5 ui p-p 0.10 ui p-p
71 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 18.8 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver shall meet the cor- responding bit error rate specification ( table 18-9 on page 69 , table 18-10 on page 69 , table 18-11 on page 70 ) when the eye pattern of the receiver test signa l (exclusive of sinusoi dal jitter) falls entirely within the unshaded portion of the receiver input compliance mask shown in figure 18-4 with the parameters specified in table 18-12 on page 71 . the eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 ohm 5% differential resis- tive load. figure 18-4. receiver input compliance mask table 18-12. receiver input compliance mask parame ters exclusive of sinusoidal jitter receiver type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud 100 800 0.275 0.400 2.5 gbaud 100 800 0.275 0.400 3.125 gbaud 100 800 0.275 0.400 1 0 0 a b 1-b 1-a time in ui receiver differential input voltage v diff max -v diff max -v diff min v diff min
72 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 18.9 measurement and test requirements since the lp-serial electrical specification are guided by the xaui electrical in terface specified in clause 47 of ieee 802.3ae-2002, the measurement and test requirements defined here are similarly guided by clause 47. in addition, the cjpat test pattern defined in annex 48a of ie ee802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements . annex 48b of ieee802.3ae-2002 is recommended as a reference for additional information on jitter test methods. 18.9.1 eye template measurements for the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data pattern for template measurements is the continuous jitter test pattern (cjpat) defined in annex 48a of ieee802.3ae. all lanes of the lp- serial link shall be active in both the transmit and re ceive directions, and opposite ends of the links shall use asynchronous clocks. four lane implementation s shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specified in annex 48a for transmission on lane 0. the amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 -12 . the eye pattern shall be measured with ac coupling and the compliance template centered at 0v differential. the left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. the load for this test sh all be 100 ohms resistive 5% differential to 2.5 ghz. 18.9.2 jitter test measurements for the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data pattern for jitter measurements is the continu- ous jitter test pattern (cjpat) patt ern defined in annex 48a of ieee802 .3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane implementations shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specifi ed in annex 48a for transmission on lane 0. jitter shall be measured with ac coupling and at 0v differential. jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be perfo rmed with a test procedure resulting in a ber curve such as that described in annex 48b of ieee802.3ae. 18.9.3 transmit jitter transmit jitter is measured at the driver output when terminated into a load of 100 ohms resistive 5% differential to 2.5 ghz. 18.9.4 jitter tolerance jitter tolerance is measured at the receiver using a jitter tolerance test signal. this signal is obtained by first producing the sum of deterministic and random jitter defined in section 8.6 and then adjusting the signal amplitude until the data eye contacts the 6 po ints of the minimum eye opening of the receive tem- plate shown in figure 8-4 and table 8-11. note that fo r this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. eye template measurement r equirements are as defined above. random jitter is calibrated using a high pass filter with a low fre quency corner at 20 mhz and a 20 db/decade roll-off below this. the required sinusoidal jitter specified in section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
73 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 19. package description this section details package parameters, pin assignments, and dimensions. 19.1 package parameters the package parameters are as provided in the following list. the package type is 29 mm x 29 mm, 783 flip chip hitce ball grid array (hitce). notes: 1. the hicte fc-cbga package is availa ble on version 2.0 and 2.1 of the device. 2. the fc-pbga package is available on only version 2.1 of the device. 3. high lead solder spheres are upon request. table 19-1. package parameters parameter cbga (1) pbga (2) package outline 29 mm x 29 mm 29 mm x 29 mm interconnects 783 783 ball pitch 1 mm 1 mm ball diameter (typical) 0.6 mm 0.6 mm solder ball (eutectic) 62% sn 36% pb 2% ag 62% sn 36% pb 2% ag solder ball high lead (3) 90% sn 10pb n.a. solder ball (lead-free) 96,5% sn 3% ag 0.5% cu 96.5% sn 3.5% ag
74 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 19.1.1 mechanical dimensions of the hitce figure 19-1 shows the mechanical dimensions and botto m surface nomenclature of the 783 hitce package. figure 19-1. mechanical dimensions of the hitce fc-cbga with full lid notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. all dimensions are symetric across the packa ge center lines, unless dimensioned otherwise. 1 a (783x) 0.3 a m bc 0.15 a m 27x 1 bottom view b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah 2345678910111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 110 24 37 6 59 81112 28 21 14 15 18 16 17 19 20 26 22 23 24 25 27 13 a d c b e j h g f m l k n w p v u t r ac ab aa y ag af ae ad ah 29 28.7 max lid zone 29 28.7 max lid zone top view a1 corner lid chamfer 0.2 4x b c 0.2 0.35 a a 783x a 0.25 a 5 seating plane 4 side view 1.63 1.37 0.6 0.35 1.32 1.08 3.38 max 3 0.65 0.5 27x 1 0.5 0.5
75 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 19.2 pinout listings note: the dma_dack [0:1] and test_ sel/ test_sel pins must be set to a proper state during por configu- ration. please refer to the pinlist table of the individual device for more details. for pc8548/47/45, gpios are still available on pci1_ad[ 63:32]/pc2_ad[31:0] pins if they are not used for pci funcationality. for mpc8545/43, etsec does not support 16 bit fifo mode. table 19-2 provides the pin-out listing for the pc8548e 783 hitce package. table 19-2. pc8548e pinout listing signal package pin number pin type power supply notes pci1 and pci2 (one 64-bit or two 32-bit) pci1_ad[63:32]/ pci2_ad[31:0] ab14, ac15, aa15, y16, w16, ab16, ac16, aa16, ae17, aa18, w18, ac17, ad16, ae16, y17, ac18, ab18, aa19, ab19, ab21, aa20, ac20, ab20, ab22, ac22, ad21, ab23, af23, ad23, ae23, ac23, ac24 i/o ov dd (16) pci1_ad[31:0] ah6, ae7, af7, ag7, ah7, af8, ah8, ae9, ah9, ac10, ab10, ad10, ag10, aa10, ah10, aa11, ab12, ae12, ag12, ah12, ab13, aa12, ac13, ae13, y14, w13, ag13, v14, ah13, ac14, y15, ab15 i/o ov dd (16) pci1_c_be [7:4]/pci2_c_be [3:0] af15, ad14, ae15, ad15 i/o ov dd (16) pci1_c_be [3:0] af9, ad11, y12, y13 i/o ov dd (16) pci1_par64/pci2_par w15 i/o ov dd pci1_gnt [4:1] ag6, ae6, af5, ah5 o ov dd (4)(8)(29) pci1_gnt0 ag5 i/o ov dd pci1_irdy af11 i/o ov dd (2) pci1_par ad12 i/o ov dd pci1_perr ac12 i/o ov dd (2) pci1_serr v13 i/o ov dd (2)(3) pci1_stop w12 i/o ov dd (2) pci1_trdy ag11 i/o ov dd (2) pci1_req [4:1] ah2, ag4, ag3, ah4 i ov dd pci1_req0 ah3 i/o ov dd pci1_clk ah26 i ov dd (32) pci1_devsel ah11 i/o ov dd (2) pci1_frame ae11 i/o ov dd (2) pci1_idsel ag9 i ov dd pci1_req64 /pci2_frame af14 i/o ov dd (2)(4)(9) pci1_ack64 /pci2_devsel v15 i/o ov dd (2)
76 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 pci2_clk ae28 i ov dd (2) pci2_irdy ad26 i/o ov dd (2) pci2_perr ad25 i/o ov dd (2) pci2_gnt [4:1] ae26, ag24, af25, ae25 o ov dd (4)(8)(29) pci2_gnt0 ag25 i/o ov dd pci2_serr ad24 i/o ov dd (2)(3) pci2_stop af24 i/o ov dd (2) pci2_trdy ad27 i/o ov dd (2) pci2_req [4:1] ad28, ae27, w17, af26 i ov dd pci2_req0 ah25 i/o ov dd ddr sdram memory interface mdq[0:63] l18, j18, k14, l13, l19, m18, l15, l14, a17, b17, a13, b12, c18, b18, b13, a12, h18, f18, j14, f15, k19, j19, h16, k15, d17, g16, k13, d14, d18, f17, f14, e14, a7, a6, d5, a4, c8, d7, b5, b4 , a2, b1, d1, e4, a3, b2, d2, e3, f3, g4, j5 , k5, f6, g5, j6, k4, j1, k2, m5, m3, j3, j2, l1, m6 i/o gv dd mecc[0:7] h13, f13, f11, c11, j13, g13, d12, m12 i/o gv dd mdm[0:8] m17, c16, k17, e16, b6, c4, h4, k1, e13 o gv dd mdqs[0:8] m15, a16, g17, g 14, a5, d3, h1, l2, c13 i/o gv dd mdqs[0:8] l17, b16, j16, h1 4, c6, c2, h3, l4, d13 i/o gv dd ma[0:15] a8, f9, d9, b9, a9, l10, m10, h10, k10, g10, b8, e10, b1 0, g6, a10, l11 ogv dd mba[0:2] f7, j7, m11 o gv dd mwe e7 o gv dd mcas h7 o gv dd mras l8 o gv dd mcke[0:3] f10, c10, j11, h11 o gv dd (10) mcs [0:3] k8, j8, g8, f8 o gv dd mck[0:5] h9, b15, g2, m9, a14, f1 o gv dd mck [0:5] j9, a15, g1, l9, b14, f2 o gv dd modt[0:3] e6, k6, l7, m7 o gv dd mdic[0:1] a19, b19 i/o gv dd (30) local bus controller interface table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
77 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] lad[0:31] e27, b20, h19, f25, a20, c19, e28, j23, a25, k22, b28, d27, d19, j22, k20, d28, d25, b25, e22, f22, f21, c25, c22, b23, f20, a23, a22, e19, a21, d21, f19, b21 i/o bv dd ldp[0:3] k21, c28, b26, b22 i/o bv dd la[27] h21 o bv dd (4)(8) la[28:31] h20, a27, d26, a28 o bv dd (4)(6)(8) lcs [0:4] j25, c20, j24, g26, a26 o bv dd lcs5 /dma_dreq2 d23 i/o bv dd (1) lcs6 /dma_dack2 g20 o bv dd (1) lcs7 /dma_ddone2 e21 o bv dd (1) lwe0 /lbs0 /lsddqm[0] g25 o bv dd (4)(8) lwe1 /lbs1 /lsddqm[1] c23 o bv dd (4)(8) lwe2 /lbs2 /lsddqm[2] j21 o bv dd (4)(8) lwe3 /lbs3 /lsddqm[3] a24 o bv dd (4)(8) lale h24 o bv dd (4)(7)(8) lbctl g27 o bv dd (4)(7)(8) lgpl0/lsda10 f23 o bv dd (4)(8) lgpl1/lsdwe g22 o bv dd (4)(8) lgpl2/loe /lsdras b27 o bv dd (4)(7)(8) lgpl3/lsdcas f24 o bv dd (4)(8) lgpl4/lgta /lupwait/lpbse h23 i/o bv dd lgpl5 e26 o bv dd (4)(8) lcke e24 o bv dd lclk[0:2] e23, d24, h22 o bv dd lsync_in f27 i bv dd lsync_out f28 o bv dd dma dma_dack [0:1] ad3, ae1 o ov dd (4)(8)(35) dma_dreq [0:1] ad4, ae2 i ov dd dma_ddone [0:1] ad2, ad1 o ov dd programmable interrupt controller ude ah16 i ov dd mcp ag19 i ov dd irq[0:7] ag23, af18, ae18, af20, ag18, af17, ah24, ae20 iov dd table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
78 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 irq[8] af19 i ov dd irq[9]/dma_dreq3 af21 i ov dd (1) irq[10]/dma_dack3 ae19 i/o ov dd (1) irq[11]/dma_ddone3 ad20 i/o ov dd (1) irq_out ad18 o ov dd (2)(3) ethernet management interface ec_mdc ab9 o ov dd (4)(8) ec_mdio ac8 i/o ov dd gigabit reference clock ec_gtx_clk125 v11 i lv dd three-speedethernet controll er (gigabit ethernet 1) tsec1_rxd[7:0] r5, u1, r3, u2, v3, v1, t3, t2 i lv dd tsec1_txd[7:0] t10, v7, u 10, u5, u4, v6, t5, t8 o lv dd (4)(8) tsec1_col r4 i lv dd tsec1_crs v5 i/o lv dd (18) tsec1_gtx_clk u7 o lv dd tsec1_rx_clk u3 i lv dd tsec1_rx_dv v2 i lv dd tsec1_rx_er t1 i lv dd tsec1_tx_clk t6 i lv dd tsec1_tx_en u9 o lv dd (24) tsec1_tx_er t7 o lv dd three-speed ethernet controller (gigabit ethernet 2) tsec2_rxd[7:0] p2, r2, n1, n2, p3, m2, m1, n3 i tsec2_txd[7:0] n9, n10, p8, n7, r9, n5, r8, n6 o tsec2_col p1 i tsec2_crs r6 i/o tsec2_gtx_clk p6 o tsec2_rx_clk n4 i tsec2_rx_dv p5 i tsec2_rx_er r1 i lv dd tsec2_tx_clk p10 i lv dd tsec2_tx_en p7 o lv dd (24) tsec2_tx_er r10 o lv dd (4)(8)(27) three-speed ethernet controller (gigabit ethernet 3) table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
79 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] tsec3_txd[3:0] v8, w10, y10, w7 o tv dd (4)(8)(23) tsec3_rxd[3:0] y1, w3, w5, w4 i tv dd tsec3_gtx_clk w8 o tv dd tsec3_rx_clk w2 i tv dd tsec3_rx_dv w1 i tv dd tsec3_rx_er y2 i tv dd tsec3_tx_clk v10 i tv dd tsec3_tx_en v9 o tv dd (24) three-speed ethernet controller (gigabit ethernet 4) tsec4_txd[3:0]/t sec3_txd[7:4] ab8, y7, aa7, y8 o tv dd (1)(4)(8)(23) tsec4_rxd[3:0]/tsec3_rxd[7 :4] aa1, y3, aa2, aa4 i tv dd (1) tsec4_gtx_clk aa5 o tv dd tsec4_rx_clk/tsec3_col y5 i tv dd (1) tsec4_rx_dv/tsec3_crs aa3 i/o tv dd (1)(25) tsec4_tx_en/tsec3_tx_er ab6 o tv dd (1)(24) duart uart_cts [0:1] ab3, ac5 i ov dd uart_rts [0:1] ac6, ad7 o ov dd uart_sin[0:1] ab5, ac7 i ov dd uart_sout[0:1] ab7, ad8 o ov dd i 2 c interface iic1_scl ag22 i/o ov dd (3)(22) iic1_sda ag21 i/o ov dd (3)(22) iic2_scl ag15 i/o ov dd (3)(22) iic2_sda ag14 i/o ov dd (3)(22) serdes sd_rx[0:7] m28, n26, p28, r26, w26, y28, aa26, ab28 i xv dd sd_rx [0:7] m27, n25, p27, r25, w25, y27, aa25, ab27 i xv dd sd_tx[0:7] m22, n20, p22, r20, u20, v22, w20, y22 o xv dd sd_tx [0:7] m23, n21, p23, r21, u21, v23, w21, y23 o xv dd sd_pll_tpd u28 o xv dd (19) sd_ref_clk t28 i xv dd sd_ref_clk t27 i xv dd reserved ac1, ac3 ?? (2) reserved m26, v28 ?? (33) table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
80 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 reserved m25, v27 ?? (28) reserved m20, m21, t22, t23 ?? (31) general-purpose output gpout[24:31] k26, k25, h27, g28, h25, j26, k24, k23 o bv dd system control hreset ag17 i ov dd hreset_req ag16 o ov dd (23) sreset ag20 i ov dd ckstp_in aa9 i ov dd ckstp_out aa8 o ov dd (2)(3) debug trig_in ab2 i ov dd trig_out/ready/quiesce ab1 o ov dd (5)(8)(17) (23) msrcid[0:1] ae4, ag2 o ov dd (4)(5)(8) msrcid[2:4] af3, af1, af2 o ov dd (5)(17)(23) mdval ae5 o ov dd (5) clk_out ae21 o ov dd (10) clock rtc af16 i ov dd sysclk ah17 i ov dd jtag tck ag28 i ov dd tdi ah28 i ov dd (11) tdo af28 o ov dd (10) tms ah27 i ov dd (11) trst ah23 i ov dd (11) dft l1_tstclk ac25 i ov dd (20) l2_tstclk ae22 i ov dd (20) lssd_mode ah20 i ov dd (20) test_sel ah14 i ov dd (20) thermal management therm0 ag1 ? (13) therm1 ah1 ? (13) table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
81 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] power management asleep ah18 o ov dd (8)(17)(23) power and ground signals gnd a11, b7, b24, c1, c3, c5, c12, c15, c26, d8, d11, d16, d20, d22, e1, e5, e9, e12, e15, e17, f4, f26, g1 2, g15, g18, g21, g24, h2, h6, h8, h28, j4 , j12, j15, j17, j27, k7, k9, k11, k27, l3, l5, l12, l16, n11, n13, n15, n17, n19, p4, p9, p12, p14, p16, p18, r11, r13, r15, r 17, r19, t4, t12, t14, t16, t18, u8, u11, u13, u15, u17, u19, v4, v12, v18, w6, w19, y4, y9, y1 1, y19, aa6, aa14, aa17, aa22, aa23, ab4, ac2, ac11, ac19, ac26, ad5, ad9, ad22, ae3, ae14, af6, af10, af13, ag8, ag27 k28, l24, l26, n24, n27, p25, r28, t24, t26, u24, v25, w28, y24, y26, aa24, aa27, ab25, ac28 l21, l23, n22, p20, r23, t21, u22, v20, w23, y21 u27 ?? ovdd v16, w11, w14, y18, aa13, aa21, ab11, ab17, ab24, ac4, ac9, ac21, ad6, ad13, ad17, ad19, ae10, ae8 , ae24, af4, af12, af22, af27, ag26 power for pci and other standards (3.3v) ov dd lvdd n8, r7, t9, u6 power for tsec1 and tsec2 (2.5v ,3.3v) lv dd tvdd w9, y6 power for tsec3 and tsec4 (2,5v, 3.3v) tv dd gvdd b3, b11, c7, c9, c14, c17, d4, d6, d10, d15, e2, e8, e11, e18, f5, f12, f16, g3, g7, g9, g11, h5, h12, h15, h17, j10, k3, k12, k16, k18, l6, m4, m8, m13 power for ddr1 and ddr2 dram i/ovoltage (1.8v,2.5v) gv dd bvdd c21, c24, c27, e20, e25, g19, g23, h26, j20 power for local bus (1.8v, 2.5v, 3.3v) bv dd vdd m19, n12, n14, n16, n18, p11, p13, p15, p17, p19, r12, r14, r16, r18, t11, t13, t15, t17, t19, u12, u14, u16, u18, v17, v19 power for core (1.1v) v dd table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
82 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ? ) be placed on this pin to ov dd . 3. this pin is an open drain signal. svdd l25, l27, m24, n28, p24, p26, r24, r27, t25, v24, v26, w24, w27, y25, aa28, ac27 core power for serdes transceivers (1.1v) sv dd xvdd l20, l22, n23, p21, r22, t20, u23, v21, w22, y20 pad power for serdes transceivers (1.1v) xv dd avdd_lbiu j28 power for local bus pll (1.1v) (21) avdd_pci1 ah21 power for pci1 pll (1.1v) (21) avdd_pci2 ah22 power for pci2 pll (1.1v) (21) avdd_core ah15 power for e500 pll (1.1v) (21) avdd_plat ah19 power for ccb pll (1.1v) (21) avdd_srds u25 power for srdspll (1.1v) (21) sensevdd m14 o v dd (12) sensevss m16 (12) analog signals mv ref a18 i reference voltage signal for ddr mv ref sd_imp_cal_rx l28 i 200 ? to gnd sd_imp_cal_tx ab26 i 100 ? to gnd sd_pll_tpa u26 o (19) table 19-2. pc8548e pinout listing (continued) signal package pin number pin type power supply notes
83 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 4. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7 k ? pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 5. treat these pins as no connects (nc) unless using debug address functionality. 6. the value of la[28:31] during reset sets the ccb cl ock to sysclk pll ratio. these pins require 4.7 k ? pull-up or pull-down resistors. see section 20.2 ?ccb/sysclk pll ratio? on page 85 . 7. the value of lale, lgpl2 and lbctl at reset set the e500 co re clock to ccb clock pll ratio. these pins require 4.7 k ? pull-up or pull-down resistors. see the section 20.3 ?e500 core pll ratio? on page 86 . 8. functionally, this pin is an output, but st ructurally it is an i/o be cause it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for boundary scan. 9. this pin functionally requires a pull-up resistor, but during re set it is a configuration inpu t that controls 32- vs. 64-bit pci operation. therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-b it pci device. refer to the pci specification. 10. this output is actively driven during reset rather than being three-stated during reset. 11. these jtag pins have weak internal pull-up p-fets that are always enabled. 12. these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 13. internal thermally sensitive resistor. 14. no connections should be made to these pins if they are not used. 15. these pins are not connected for any use. 16. pci specifications recommend that a weak pull-up resistor (2?10 k ? ) be placed on the higher order pins to ov dd when using 64-bit buffer mode (pins pci_ad[63:32] and pci1_c_be [7:4]). 17. if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a sa fe state during reset. 18. this pin is only an output in fifo mode when used as rx flow control. 19. do not connect. 20. these are test signals for factory use only and must be pulled up (100 . - 1 k . ) to ov dd for normal machine operation. 21. independent supplies derived from board v dd . 22. recommend a pull-up resistor (~1 k . ) b placed on this pin to ov dd . 23. the following pins must not be pulled down during power-on reset: tsec3_txd[3], tsec4_txd3/tsec3_txd7, hreset_req, trig_o ut/ready/quiesce , msrcid[2:4], asleep. for rev 2.0 silicon, cfg_srds_en added to tsec4_txd[2]/tsec3_txd[6] -this por conf ig powers down the serdes block entirely if pulled down. if the serdes is going to be used in any way, then this pin should be pulled up or it can be left without a pullup or pulldown. for rev. 1.x/rev 1.1.x silicon, tsec4_txd[2: 3] pin values during por configuration are don?t care. 24. this pin requires an external 4.7 k ? pull-down resistor to prevent phy from seei ng a valid transmit enable before it is actively driven. 25. this pin is only an output in etsec3 fi fo mode when used as rx flow control. 26. these pins should be connected to xv dd . 27. tsec2_txd1, tsec2_tx_er are mult iplexedas cfg_dram_type[ 0:1]. they must be valid at power-up, even before hreset assertion. 28. these pins should be pulled to ground through a 300 ? (10%) resistor. 29. when a pci block is disabled, either the por config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other pci devi ce connected on the pci bus, or leave the pci n_ad pins as "no connect" or terminated through 2?10 k ? pull-up resistors with the default of internal arbiter if the pci n_ad pins are not con- nected to any other pci device. the pci block will drive the pci n_ ad pins if it is configured to be the pci arbiter, through por config pins, irrespective of whether it is disabled via the devdisr register or not. it may cause contention if there is any other pci device connected on the bus. 30. mdic0 is grounded through an 18.2 ? precision 1% resistor and mdic1 is connected to gv dd through an 18.2 ? precision 1% resistor. these pins are used for automatic calibration of the ddr ios.
84 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 31. these pins should be left floating. 32. if pci1 or pci2 is configured as pci asynchronous mode, a valid clock must be provided on pin pci1_clk or pci2_clk. otherwise the processor will not boot up. 33. these pins should be connected to gnd. 34. this pin requires an external 4.7 k ? resistor to gnd. 35. for rev. 2.0 silicon, dma_dack [0:1] must be 0b11 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 36. if these pins are not used as gpinn (general-purpose in put), they should be pulled low (to gnd) or high (to lv dd ) through 2?10 k ? resistors. 37. these should be pulled low to gnd through 2?10 k ? resistors if they are not used. 38. these should be pulled low or high to lv dd through 2?10 k ? resistors if they are not used. 39. for rev. 2.0 silicon, dma_dack [0:1] must be 0b10 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 40. for rev. 2.0 silicon, dma_dack [0:1] must be 0b01 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 41. for rev. 2.0 silicon, dma_dack [0:1] must be 0b11 during por configuration; for rev. 1.x silicon, the pin values during por -+configuration are don?t care. 42. this is a test signal for factory use only and must be pulled down (100 ? ? 1 k ? ) to gnd for normal machine operation. 43. these pins should be pulled high to ov dd through 2?10 k ? resistors. 44. if these pins are not used as gpinn (general-purpose in put), they should be pulled low (to gnd) or high (to ov dd ) through 2?10 k ? resistors. 45. this pin must not be pulled down during por configuration. 46. these should be pulled low or high to ov dd through 2?10 k ? resistors.
85 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 20. clocking this section describes the pll configuration of the pc8548e. note that the platform clock is identical to the core complex bus (ccb) clock. 20.1 clock ranges table 20-1 provides the clocking specifications for the processor cores and table 20-2 provides the clocking specifications for the memory bus. notes: 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be ch osen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not e xceed their respective maximum or minimum operating fre- quencies. refer to section 20.2 ?ccb/sysclk pll ratio? on page 85 , and section 20.3 ?e500 core pll ratio? on page 86 , for ratio settings. 2. the minimum e500 core frequency is based on the minimum platform frequency of 266 mhz. notes: 1. caution: the ccb clock to sysclk ratio and e500 core to cc b clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequen cy do not exceed their respective maximum or minimum operating frequencies. refer to section 20.2 ?ccb/sysclk pll ratio? on page 85 , and section 20.3 ?e500 core pll ratio? on page 86 , for ratio settings. 2. the memory bus speed is half of the ddr/ddr2 dat a rate, hence, half of the platform clock frequency. 20.2 ccb/sysclk pll ratio the ccb clock is the clock that drives the e500 core complex bus (ccb), and is also called the platform clock. the frequency of the ccb is set using the following reset signals, as shown in table 20-3 : sysclk input signal binary value on la[28:31] at power up note that there is no default for this pll ratio; th ese signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the bus frequency, since the frequency must equal the ddr data rate. table 20-1. processor core clocking specifications characteristic maximum processor core frequency unit notes 1000 mhz 1200 mhz 1333 mhz minmaxminmaxminmax e500 core processor frequency 533 1000 533 1200 533 1333 mhz (1)(2) table 20-2. memory bus clocking specifications characteristic maximum processor core frequency unit notes 1000, 1200, 1333 mhz min max memory bus clock speed 133 266 mhz (1)(2)
86 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 for specifications on the pci_clk, refer to the pci 2.2 specification. 20.3 e500 core pll ratio table 20-4 describes the clock ratio between the e500 core complex bus (ccb) and the e500 core clock. this ratio is determined by the binary value of lbctl, lale and lgpl2 at power up, as shown in table 20-4 . table 20-3. ccb clock ratio binary value of la[28:31] signals ccb:sysclk ratio 0000 16:1 0001 reserved 0010 2:1 0011 3:1 0100 4:1 0101 5:1 0110 6:1 0111 reserved 1000 8:1 1001 9:1 1010 10:1 1011 reserved 1100 12:1 1101 20:1 1110 reserved 1111 reserved table 20-4. e500 core to ccb clock ratio binary value of lbctl, lale, lgpl 2 signals e500 core:ccb clock ratio 000 4:1 001 9:2 010 1:1 011 3:2 100 2:1 101 5:2 110 3:1 111 7:2
87 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 20.4 frequency options 20.4.1 sysclk to platform frequency options table 20-5 shows the expected frequency values for the platform frequency when using a ccb clock to sysclk ratio in comparison to the memory bus clock speed. table 20-5. frequency options of sysclk with respect to memory bus speeds ccb to sysclk ratio sysclk (mhz) 16.66 25 33.33 41.66 66.66 83 100 111 133.33 166 platform/ccb frequency (mhz) 2 267 332 3 300 333 400 498 4 267 333 400 445 533 5 333 415 500 6400500 8 267 333 533 9300375 10 333 417 12 300 400 500 16 267 400 533 20 333 500
88 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 21. thermal this section describes the thermal specifications of the pc8548. 21.1 thermal for revision 2.0 silic on hicte fc-cbga with full lid this section describes the thermal specifications for the hicte fc-cbga pa ckage for revision 2.0 silicon. table 21-1 shows the package thermal characteristics. notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (b oard) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2. per jedec jesd51-6 with the board (jesd51-7) horizontal. 3. thermal resistance between the die and the printed circui t board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between th e die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). the cold plate temperature is used for the ca se temperature, measured value includes the thermal resis- tance of the interface layer. 21.2 thermal for version 2.1 si licon fc-pbga with full lid this section describes t he thermal specifications for the fc-pbga packag e for revision 2.1 silicon. table 21-2 shows the package thermal characteristics. table 21-1. package thermal characteri stics for hicte fc-cbga characteristic jedec board symbol value unit notes die junction-to-ambient (natural convection) single-layer board (1s) r ja 17 c/w (1)(2) die junction-to-ambient (natural convection) four-layer board (2s2p) r ja 12 c/w (1)(2) die junction-to-ambient (200 ft/min) single-layer board (1s) r ja 11 c/w (1)(2) die junction-to-ambient (200 ft/min) four-layer board (2s2p) r ja 8c/w (1)(2) die junction-to-board n/a r jb 3c/w (3) die junction-to-case n/a r jc 0.8 c/w (4) table 21-2. package thermal characteri stics for hicte fc-pbga characteristic jedec board symbol value unit notes die junction-to-ambient (natural convection) single-layer board (1s) r ja 18 c/w (1)(2) die junction-to-ambient (natural convection) four-layer board (2s2p) r ja 13 c/w (1)(2) die junction-to-ambient (200 ft/min) single-layer board (1s) r ja 13 c/w (1)(2) die junction-to-ambient (200 ft/min) four-layer board (2s2p) r ja 9c/w (1)(2) die junction-to-board n/a r jb 5c/w (3) die junction-to-case n/a r jc 0.8 c/w (4)
89 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (b oard) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2. per jedec jesd51-6 with the board (jesd51-7) horizontal. 3. thermal resistance between the die and the printed circui t board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between th e die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). the cold plate temperature is used for the ca se temperature, measured value includes the thermal resis- tance of the interface layer. 21.3 heat sink solution every system application has different conditions that the thermal management solution must solve. as such, providing a recommended heat sink has not bee n found to be very useful. when a heat sink is chosen, give special consideration to the mounting technique. mounting the heat sink to the printed cir- cuit board is the recommended procedure using a maximum of 10 lbs. force (45 newtons) perpendicular to the package and bo ard. clipping the heat sink to the package is not recommended. 22. system design information this section provides electrical and thermal design recommendations fo r successful application of the pc8548e. 22.1 system clocking this device includes five plls, as follows: 1. the platform pll generates th e platform clock from the exte rnally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio con- figuration bits as described in section 20.2 ?ccb/sysclk pll ratio? on page 85 . 2. the e500 core pll generates the core clock as a slave to the platform clock. the frequency ratio between the e500 core clock and the platform clock is selected using the e500 pll ratio configuration bits as described in section 20.3 ?e500 core pll ratio? on page 86 . 3. the pci pll generates the clocking for the pci bus 4. the local bus pll generates the clock for the local bus. 5. there is a pll for the serdes block. 22.2 power supply design 22.2.1 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd _plat, av dd _core, av dd _pci, av dd _lbiu, and av dd _srds respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits per pll power supply as illustrated in figure 22-1 , one to each of the av dd pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the pl ls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacit ors with minimum effective series inductance (esl).
90 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple sm all capacitors of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possi ble to route directly from the capacitors to the av dd pin, which is on the periphery of 783 hitce the footprint, without the inductance of vias. figure 22-1 shows the pll power supply filter circuits. figure 22-1. pc8548e pll power supply filter circuit the av dd _srds signal provides power for the analog portions of the serd es pll. to ensure stability of the internal clock, the power supplied to the pll is f iltered using a circuit similar to the one shown in fol- lowing figure. for maximum effectiveness, the filter circuit is placed as closely as possible to the av dd _srds ball to ensure it filters out as much noise as possible. the ground connection should be near the av dd _srds ball. the 0.003 f capacitor is closest to the ball, followed by the 1 f capacitor, and finally the 1 ohm resistor to the board supply plane. the capacitors are connected from av dd _srds to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide and direct. figure 22-2. serdes pll power supply filter note: 1. an 0805 sized capacitor is reco mmended for system initial bring-up. note the following: av dd _srds should be a filtered version of sv dd . signals on the serdes interface are fed from the xv dd power plane. power: xv dd consumes less than 300 mw; sv dd + av dd _srds consumes less than 750 mw. av dd 2.2 f 2.2 f gnd low esl surface mount capacitors 10 ? v dd 2.2 f 1 0.003 f gnd 1.0 ? av dd _srds sv dd 2.2 f 1
91 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 22.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the pc8548e system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , tv dd , bv dd , ov dd , gv dd , and lv dd ,pin of the device. these decoupling capacitors should receive their power from separate v dd ,tv dd , bv dd , ov dd , gv dd , and lv dd ,and gnd power planes in t he pcb, utilizing short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may sur- round the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , tv dd , bv dd , ov dd , gv dd , and lv dd ,planes, to enable quick recharging of the smaller chip capacitors. these bulk capacit ors should have a low esr (equival ent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100?330 f (avx tps tan- talum or sanyo oscon). 22.4 serdes block power suppl y decoupling recommendations the serdes block requires a clean, tightly regulated source of power (sv dd and xv dd ) to ensure low jit- ter on transmit and reliable recovery of data in the receiver. an appropriate decoupling scheme is outlined below. only surface mount technology (smt) capacitors sh ould be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. first, the board should have at least 10 10 nf smt ceramic chip capaci tors as close as possible to the supply balls of the device. where the board ha s blind vias, these capacitors should be placed directly below the chip supply and ground connections. where the board does not have blind vias, these capacitors should be placed in a ring aroun d the device as close to the supply and ground connections as possible. second, there should be a 1 f ceramic chip capacito r on each side of the device. this should be done for all serdes supplies. third, between the device and any serdes voltage re gulator there should be a 10 f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100 f, low esr smt tantalum chip capacitor. this should be done for all serdes supplies. 22.5 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. all unused active low inputs should be tied to v dd , tv dd , bv dd , ov dd , gv dd , and lv dd , as required. all unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , tv dd , bv dd , ov dd , gv dd , and lv dd , and gnd pins of the device.
92 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 22.6 pull-up and pull-dow n resistor requirements the pc8548e requires weak pull-up resistors (2?10 k ? is recommended) on open drain type pins including i 2 c pins and mpic interrupt pins. correct operation of the jtag interface requires configuration of a group of system control pins as dem- onstrated in figure 22-5 on page 95 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spu- rious assertion will give unpredictable results. the following pins must not be pulled down dur ing power-on reset: tsec3_txd[3], hreset_req, trig_out/ready/quiesce , msrcid[2:4], asleep. the dma_dack[0:1] and test_sel/ test_sel pins must be set to a proper state during por configuration. please refer to the pinlist table of the individual device for more details. refer to the pci 2.2 specificatio n for all pull-ups required for pci. 22.7 output buffer dc impedance the pc8548e drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 22-3 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 22-3. driver impedance measurement ov dd ognd r p r n pad data sw1 sw2
93 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] table 22-1 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , 105c. note: nominal supply voltages. see table 3-1 on page 10 , t c = 105c. 22.8 configurati on pin muxing the pc8548e provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k ? on certain output pins (see customer visible configura- tion pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treat ed as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal functi on. most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k ? . this value should permit the 4.7 k ? resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform /system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. the default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disrupti on of signal quality or speed for output pins thus configured. the platform pll ratio and e500 pll ratio configuration pins are not equipped with these default pull-up devices. 22.9 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee std 1149.1 specification, but is provided on al l processors that implement the powerpc architec- ture. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signal s, generally systems will assert trst during the power- on reset flow. simply tying trst to hreset is not practical because the jtag interface is also used for accessing the common on-chip processor (cop) function. the cop function of these processors allow a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. table 22-1. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 43 target 25 target 20 target z 0 w r p 43 target 25 target 20 target z 0 w
94 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 the arrangement shown in figure 22-5 on page 95 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 22-5 on page 95 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoi nts, watchpoints, register and memory examina- tion/modification, and other standard debugger featur es. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop header; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 22-5 is com- mon to all known emulators. 22.9.1 termination of unused signals if the jtag interface and cop header will not be used, freescale recommends the following connections: trst should be tied to hreset through a 0 k ? isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 22-4 . if this is not possible, the isolatio n resistor will allow fu ture access to trst in case a jtag interface may need to be wired onto the system in future debug situations. no pull-up/pull-down is required for tdi, tms, tdo, or tck. figure 22-4. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi cop_run/stop nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
95 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] figure 22-5. jtag interface connection note: 1. the cop port and target board should be able to independently assert hreset and trst to the pro- cessor in order to fully control the processor as shown here. 2. populate this with a 10 ? resistor for short-circui t/current-limiting protection. 3. the key location (pin 14) is not ph ysically present on the cop header. 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for improved signal integrity. 5. this switch is included as a precaution for bsdl te sting. the switch should be closed to position a dur- ing bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed to position b. 6. asserting sreset causes a machine check interrupt to the e500 core. hreset cop_hreset 13 cop_sreset sreset nc 11 cop_vdd_sense 2 6 5 15 cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 cop header 14 3 trst 1 ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 cop connector pysical pinout 2 nc sreset nc ov dd hreset 1 tck 4 5 6 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 ? 10 k ? from target board sources (if any) key no pin b a
96 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 22.10 guidelines for high-s peed interface termination 22.10.1 serdes interface entirely unused if the high-speed serdes interface is not used at all, the unused pin should be terminated as described in this section. the following pins must be left unconnected (float): sd_tx[7:0] sd_tx [7:0] reserved pins t22, t23, m20, m21 the following pins must be connected to gnd: sd_rx[7:0] sd_rx[7:0] sd_ref_clk sd_ref_clk note: it is recommended to power down the unused lane through serdescr1[0:7] register (offset = 0xe_0f08) (this prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. pins v28 and m26 must be tied to xv dd . pins v27 and m25 must be tied to gnd through a 300 ? resistor. in rev 2.0 silicon, por configuration pin cfg_s rds_en on tsec4_txd[2] /tsec3_txd[6] can be used to power down serdes block. 22.10.2 serdes interface partly unused if only part of the high speed serdes interface pins are used, the remaining high-speed serial i/o pins should be terminated as described in this section. the following pins must be left unconnected (float) if not used: sd_tx[7:0] sd_tx [7:0] reserved pins: t22, t23, m20, m21 the following pins must be connected to gnd if not used: sd_rx[7:0] sd_rx [7:0] sd_ref_clk sd_ref_clk note: it is recommended to power down the unused lane through serdescr1[0:7] register (offset = 0xe_0f08) (this prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. pins v28 and m26 must be tied to xv dd . pins v27 and m25 must be tied to gnd through a 300 ? resistor.
97 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 22.11 guideline for pci interface temination pci termination if pci 1 or pci 2 is not used at all. option 1 if pci arbiter is enabled during por, all ad pins will be driven to the stable states af ter por. therefore, all ads pins can be floating. all pci control pins can be grouped together and tied to ov dd through a single 10 k ? resistor. it is optional to disable pci block through devdisr register after por reset. option 2 if pci arbiter is disabled during por, all ad pins will be in the input stat e. therefore, all ads pins need to be grouped toget her and tied to ov dd through a single (or multiple) 10 k ? resistor(s) all pci control pins can be grouped together and tied to ov dd through a single 10k resistor it is optional to disable pci block through devdisr register after por reset. 22.12 guideline for lbiu parity temination in lbiu parity pins are not used. here is the termination recommendation: for ldp[0:3]: tie them to ground or the power supply rail via a 4.7k resistor. for lpbse: tie it to the po wer supply rail via a 4.7k resistor (pull-up resistor). 23. definitions 23.1 life support applications these products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. 24. ordering information figure 24-1. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. xx y xx x x xx 8548 part identifier 8548e product code (1) pc(x) (2) package (1) revision level (1) temperature range (1) u screening level processor frequency platform frequency blank = 2.0 a = version 2.1 v: t c = -40?c ; t j = 110?c m: t c = -55?c ; t j = 125?c gh = hitce cbga lh = hitce lga ghy = rohs bga zf = pbga av = 1500 mhz (tbc) au = 1333 mhz (tbc) at = 1200 mhz aq = 1000 mhz an = 800 mhz j = 533 mhz (tbc) g = 400 mhz blank : standard u: upscreening
98 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 25. document revision history table 25-1 provides a revision history for this hardware specification. table 25-1. document revision history revision number date substantive change(s) c 04/2008 tc replaced by t j b 11/2007 adjusted maximum sysclk frequency down in table 6, ?sysclk ac timing specifications? per device eratum gen-13 clarified notes to table 5-2 on page 16 added section 5.4 ?pci/pci-x reference clock timing? on page 16 clarified descriptions and added pci/pci-x to table 6-2 removed support for 266 and 200 mbps data rates per device erratum gen-13 in section 7. ?ddr and ddr2 sdram? on page 18 clarified note 4 of table 7-9 on page 21 clarified the reference clock used in section 8.2 ?duart ac electric al specifications? on page 23 corrected vih(min) in table 9-1 on page 24 corrected vil(max) in table 9-2 on page 25 removed dc parameters from table 9-3 on page 26 , table 9-5 on page 27 , table 9-5 on page 27 , table 9-6 on page 28 , table 9-7 on page 29 , table 9-14 on page 35 , table 9-11 on page 33 , table 9-13 on page 34 and table 9-14 on page 35 corrected v ih (min) in table 10-1, ?mii management dc electrical characteristics,? on page 36 corrected t mdc (min) in table 10-2, ?mii management ac timing specifications (at recommended operating conditions with ovdd is 3.3v 5%),? on page 37 updated parameter descriptions for t lbivkh1 , t lbivkh2 , t lbixkh1 , and t lbixkh2 in table 11-4, ?local bus timing parameters (bvdd = 2.5v): pll enabled,? on page 40 and table 11-5, ?local bus timing parameters: pll bypassed,? on page 42 updated parameter descriptions for t lbivkh1 , t lbivkl2 , t lbixkh1 , and t lbixkl2 in table 11-5, ?local bus timing parameters: pll bypassed,? on page 42 note that t lbivkl2 and t lbixkl2 were previously labeled t lbivkh2 and t lbixkh2 added lupwait signal to figure 11-2 on page 41 and figure 11-4 on page 44 . added lgta signal to figure 11-4 , figure 11-6 , figure 11-5 and figure 11-7 corrected lupwait assertion in figure 11-5 and figure 11-7 clarified the pci reference clock in section 15.2 ?pci/pci-x ac electr ical specifications? on page 53 updated figure 16-1 on page 56 added section 19.1 ?package parameters? on page 73 added pbga thermal information in section 21.2 ?thermal for version 2. 1 silicon fc-pbga with full lid? on page 88 updated section 21.3 ?heat sink solution? on page 89 a 08/2007 initial revision
i 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] table of contents features ................. .............. .............. .............. .............. .............. ............. 1 description ......... ................. .............. .............. .............. .............. ............. 2 screening ........... ................. .............. .............. .............. .............. ............. 2 1 pc8548e architecture general overview .. ................. .............. ............. 2 2 features overview .............. .............. .............. .............. .............. ............. 3 3 electrical characteristics ... .............. .............. .............. .............. ............. 9 3.1 overall dc electrical characteristics ..................................................................... 9 3.2 detailed specification ........................................................................................... 10 3.3 applicable documents .......................................................................................... 10 3.3.1 absolute maximum ratings ................................................................... 10 3.3.2 recommended operating conditions ................................................... 11 3.3.3 output driver characteristics ................................................................ 13 3.4 power sequencing ............................................................................................... 13 4 power characteristics ........ .............. .............. .............. .............. ........... 14 5 input clocks .............. ................. ................ ................. ................ ........... 15 5.1 system clock timing ............................................................................................ 15 5.2 real time clock timing ....................................................................................... 15 5.3 etsec gigabit reference clock timing .............................................................. 16 5.4 pci/pci-x reference clock timing ..................................................................... 16 5.5 platform to fifo restrictions ................................................................................ 17 5.6 platform frequency requirements for pci-express and serial rapidio ............. 17 5.7 other input clocks ................................................................................................ 17 6 reset initialization ............ .............. .............. .............. .............. ........... 17 7 ddr and ddr2 sdram .......... ................. ................ ................. ............. 18 7.1 ddr sdram dc electrical characteristics ......................................................... 18 7.2 ddr sdram ac electrical characteristics ......................................................... 20 7.2.1 ddr sdram input ac timing specifications ....................................... 20 7.2.2 ddr sdram output ac timing specifications .................................... 21 8 duart .............. ................ ................. .............. .............. .............. ........... 23 8.1 duart dc electrical characteristics .................................................................. 23 8.2 duart ac electrical specifications .................................................................... 23
ii 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 9 ethernet: enhanced three-s peed ethernet (etsec), mii management ........... ................ ................ ................. .............. ........... 24 9.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps) gmii/mii/tbi/ rgmii/rtbi/rmii electrical characteristics .............................. 24 9.1.1 etsec dc electrical characteristics ....................................................24 9.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications ............. 25 9.2.1 fifo ac specifications ......................................................................... 25 9.2.2 gmii ac timing specifications .............................................................. 27 9.2.2.1 gmii transmit ac timing specifications ............................... 27 9.2.2.2 gmii receive ac timing specifications ................................ 28 9.2.3 mii ac timing specifications ................................................................ 29 9.2.3.1 mii receive ac timing specifications ................................... 29 9.2.3.2 mii receive ac timing specifications ................................... 30 9.2.4 tbi ac timing specifications ................................................................ 31 9.2.4.1 tbi transmit ac timing specifications ................................. 31 9.2.4.2 tbi receive ac timing specifications .................................. 32 9.2.5 tbi single-clock mode ac specifications ............................................. 32 9.2.6 rgmii and rtbi ac timing specifications ........................................... 33 9.2.7 rmii ac timing specifications .............................................................. 34 9.2.7.1 rmii transmit ac timing specifications ............................... 34 9.2.7.2 rmii receive ac timing specifications ................................ 35 10 ethernet management interf ace electrical characte ristics ............... 36 10.1 mii management dc electrical characteristics .................................................. 36 10.2 mii management ac electrical specifications ....................................................37 11 local bus ............... .............. .............. .............. .............. .............. ........... 38 11.1 local bus dc electrical characteristics ............................................................. 38 11.2 local bus ac electrical specifications ............................................................... 39 12 programmable interrupt contro ller ............... .............. .............. ........... 47 13 jtag ...................... .............. .............. .............. .............. .............. ........... 48 13.1 jtag dc electrical characteristics .................................................................... 48 13.2 jtag ac electrical specifications ..................................................................... 48 14 i 2 c ................. ................. ................ ................ ................. .............. ........... 50 14.1 i 2 c dc electrical characteristics ........................................................................ 50 14.2 i 2 c ac electrical specifications .......................................................................... 51
iii 0831c?hirel?04/08 e2v semiconductors sas 2008 pc8548e [preliminary] 15 pci/pci-x ............... .............. .............. .............. .............. .............. ........... 52 15.1 pci/pci-x dc electrical characteristics ............................................................ 52 15.2 pci/pci-x ac electrical specifications .............................................................. 53 16 high-speed interfaces 56 16.1 dc requirements for serdes reference clocks ............................................... 56 16.2 spread spectrum clock ..................................................................................... 56 17 pci express ........... .............. .............. .............. .............. .............. ........... 56 17.1 dc requirements for pci express sd_ref_clk and sd_ref_clk ............. 56 17.2 ac requirements for pci express serdes clocks ............................................ 57 17.3 clocking dependencies ...................................................................................... 57 17.4 physical layer specifications ............................................................................. 57 17.4.1 differential transmitter (tx) output ....................................................57 17.4.2 transmitter compliance eye diagrams ............................................... 59 17.4.3 differential receiver (rx) input specifications .................................... 60 17.5 receiver compliance eye diagrams .................................................................. 62 17.5.1 compliance test and measurement load .......................................... 63 18 serial rapidio ................ ................ ................. .............. .............. ........... 63 18.1 dc requirements for serial rapidio sd_ref_clk and sd_ref_clk .......... 63 18.2 ac requirements for serial rapidio sd_ref_clk and sd_ref_clk .......... 64 18.3 signal definitions ................................................................................................ 64 18.4 equalization ........................................................................................................ 65 18.5 explanatory note on transmitter and receiver specifications .......................... 65 18.6 transmitter specifications .................................................................................. 65 18.7 receiver specifications ...................................................................................... 69 18.8 receiver eye diagrams ...................................................................................... 71 18.9 measurement and test requirements ............................................................... 72 18.9.1 eye template measurements ............................................................. 72 18.9.2 jitter test measurements .................................................................... 72 18.9.3 transmit jitter ...................................................................................... 72 18.9.4 jitter tolerance .................................................................................... 72 19 package description .............. ................. ................ ................. ............. 73 19.1 package parameters .......................................................................................... 73 19.1.1 mechanical dimensions of the hitce ................................................. 74 19.2 pinout listings .................................................................................................... 75
iv 0831c?hirel?04/08 pc8548e [preliminary] e2v semiconductors sas 2008 20 clocking .............. ................. .............. .............. .............. .............. ........... 85 20.1 clock ranges ..................................................................................................... 85 20.2 ccb/sysclk pll ratio ... ................. ................ ............. ............. ............ .......... 85 20.3 e500 core pll ratio .......................................................................................... 86 20.4 frequency options ............................................................................................. 87 20.4.1 sysclk to platform frequency options ................................................ 87 21 thermal ............. ................ ................. .............. .............. .............. ........... 88 21.1 thermal for revision 2.0 silicon hicte fc-cbga with full lid ........................ 88 21.2 thermal for version 2.1 silicon fc-pbga with full lid ..................................... 88 21.3 heat sink solution ..............................................................................................89 22 system design information ... ................. ................ ................. ............. 89 22.1 system clocking ................................................................................................. 89 22.2 power supply design ......................................................................................... 89 22.2.1 pll power supply filtering .................................................................89 22.3 decoupling recommendations .......................................................................... 91 22.4 serdes block power supply decoupling recommendations ............................ 91 22.5 connection recommendations .......................................................................... 91 22.6 pull-up and pull-down resistor requirements .................................................. 92 22.7 output buffer dc impedance ............................................................................. 92 22.8 configuration pin muxing ................................................................................... 93 22.9 jtag configuration signals ............................................................................... 93 22.9.1 termination of unused signals ........................................................... 94 22.10 guidelines for high-speed interface termination ............................................ 96 22.10.1 serdes interface entirely unused ..................................................... 96 22.10.2 serdes interface partly unused ........................................................ 96 22.11 guideline for pci interface temination ............................................................ 97 22.12 guideline for lbiu parity temination ............................................................... 97 23 definitions ............. .............. .............. .............. .............. .............. ........... 97 23.1 life support applications .................................................................................... 97 24 ordering information ............ .............. .............. .............. .............. ......... 97 25 document revision history .. ............. .............. .............. .............. ......... 98 table of contents ................. .............. .............. .............. .............. ............ i
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